The V104 10 Bit LVDS Receiver for Video is designed
to support video data transmission between display
engines and video processing engines for television
and projector applications. The V104 supports up to
WXGA resolutions for Plasma, Rear Projection, Front
Projection, CRT and LCD applications.
The V104 converts the 6 LVDS (Low Voltage
Differential Signaling) video data stream pairs to 35
CMOS/TTL data bits with a rising or falling edge clock.
The clock edge selection is performed using a
dedicated pin.
In conjunction with the V103 transmitter, the V104 can
transmit 10 bits per color (R, G, B) along with 5 bits of
control and timing data (HSYNC, VSYNC, DE, CNTL1,
CNTL2) over a low EMI, low bus width connection
including connectors and standard LVDS cabling.
PRELIMINARY
Features
•
•
•
•
•
•
•
•
•
Pin & function compatible with the THC63LVD104A
Wide pixel clock range: 8 - 90 MHz
Supports resolutions from 480p to WXGA
Internal PLL does not require external loop filter
Clock edge selection for TTL alignment selectable
Power down mode
Single 3.3V supply
Low power consumption CMOS design
64-pin TQFP lead free package
Block Diagram
LVDS Input
RA+/-
7
CMOS/TTL Output
7
RA6-RA0
RB6-RB0
RC6-RC0
RD6-RD0
RE6-RE0
CLKOUT
RB+/-
RC+/-
RD+/-
RE+/-
RCLK+/-
(8 to 90 MHz)
Serial to
Parallel
7
7
7
PLL
CMOS/TTL Input
TEST
PD
OE
R/F
V104 Datasheet
1
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V104
10 B
IT
LVDS R
ECEIVER FOR
V
IDEO
PRELIMINARY
Pin Assignment
PVCC
PGND
RE+
RE-
RD+
RD-
LGND
RCLK+
RCLK-
RC+
RC-
LVCC
RB+
RB-
RA+
RA-
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pin Descriptions
Pin
Number
50, 49
52, 51
55, 54
60, 59
62, 61
57, 56
40, 41, 42, 43,
45, 46, 47
32, 33, 34, 35,
36, 38, 39
22, 24, 25, 26,
27, 28, 29
14, 15, 17, 18,
19, 20, 21
Pin
Name
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
RE+, RE-
RCLK+, RCLK-
RA6 ~ RA0
RB6 ~ RB0
RC6 ~ RC0
RD6 ~ RD0
Pin Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
LVDS Data In
LVDS Data In
LVDS Data In
LVDS Data In
LVDS Data In
LVDS Clock In
CMOS/TTL Data Outputs
CMOS/TTL Data Outputs
CMOS/TTL Data Outputs
CMOS/TTL Data Outputs
V104 Datasheet
RD4
RD3
RD2
RD1
RD0
RC6
VCC
RC5
RC4
RC3
RC2
RC1
RC0
GND
CLKOUT
RB6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
TEST
PD
OE
R/F
RE6
RE5
RE4
VCC
RE3
RE2
RE1
RE0
RD6
RD5
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-pin TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
RA0
RA1
RA2
GND
RA3
RA4
RA5
RA6
RB0
RB1
VCC
RB2
RB3
RB4
RB5
Pin Description
2
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V104
10 B
IT
LVDS R
ECEIVER FOR
V
IDEO
Pin
Number
6, 7, 8, 10, 11,
12, 13
2
3
4
5
9, 23, 37, 48
31
1, 16, 30, 44
53
58
64
63
PRELIMINARY
Pin
Name
RE6 ~ RE0
TEST
PD
OE
R/F
VCC
CLKOUT
GND
LVCC
LGND
PVCC
PGND
Pin Type
OUT
IN
IN
IN
IN
Power
OUT
Ground
Power
Ground
Power
Ground
CMOS/TTL Data Outputs.
Not used. Tie LOW.
Pin Description
HIGH: normal operation; LOW: Power down (all outputs are “L”).
Power supply pins for TTL outputs and digital circuitry.
Clock out.
Ground pins for TTL outputs and digital circuitry.
Power supply pins for LVDS inputs.
Ground pins for LVDS inputs.
Power supply pin for PLL circuitry.
Ground pin for PLL circuitry.
PD
0
0
0
0
1
1
1
1
R/F
0
0
1
1
0
0
1
1
OE
0
1
0
1
0
1
0
1
Data Outputs (Rxn)
High impedance
All 0
High impedance
All 0
High impedance
Data Out
High impedance
Data Out
CLKOUT
High impedance
Fixed Low
High impedance
Fixed Low
High impedance
Latches output data on falling edge
High impedance
Latches output data on rising edge
**Rxn
x = A, B, C, D, E
n = 0, 1, 2, 3, 4, 5, 6
V104 Datasheet
3
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V104
10 B
IT
LVDS R
ECEIVER FOR
V
IDEO
PRELIMINARY
External Components
The V104 requires no external components.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V104. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VCC
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Receiver Input Voltage
Output Current
Storage Temperature
Junction Temperature
Soldering Temperature (10 seconds)
Maximum Power Dissipation @ +25°C
-0.3 V to +4.0 V
-0.3 V to VCC+0.3 V
-0.3 V to VCC+0.3 V
-0.3 V to VCC+0.3 V
-30 mA to 30 mA
-55 to +125°C
125°C
260°C
1.0 W
Rating
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+3.6
Units
°C
V
V104 Datasheet
4
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
V104
10 B
IT
LVDS R
ECEIVER FOR
V
IDEO
PRELIMINARY
Electrical Characteristics
VDD=3.3 V ±10%,
Ambient temperature 0 to +70°C
Parameter
CMOS/TTL DC Specifications
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Current
LVDS Receiver DC Specifications
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
TH
V
TL
I
INL
V
OC
= 1.2 V
V
OC
= 1.2 V
V
IN
= 2.4 V / 0V
V
IN
= 3.6 V
-100
±20
100
mV
mV
µA
V
IH
V
IL
V
OH
V
OL
I
INC
I
OH
= -4 mA (data)
I
OH
= -8 mA (clock)
I
OH
= -4 mA (data)
I
OH
= -8 mA (clock)
0V<VIN<VCC
2.00
GND
2.4
0.4
±10
VCC
0.80
V
V
V
V
µA
Symbol
Conditions
Min.
Typ.
Max.
Units
Parameter
Supply Current
Receiver Supply Current (Gray Scale
Pattern)
Receiver Supply Current (Checker
Pattern)
Receiver Power Down Supply Current
Symbol
I
RCCG
I
RCCW
I
RCCS
Conditions
f
CLKOUT
= 90 MHz
f
CLKOUT
= 90 MHz
PD = L
C
L
=8 pF,
V
CC
= 3.3 V
C
L
=8 pF,
V
CC
= 3.3 V
Typ.
70
112
Max.
Units
mA
mA
10
µA
V104 Datasheet
5
1/12/05
Revision 1.6
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 • t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 • ww w.i c s t . c o m
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