CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
At T
A
= Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges:
LIMITS
CDP6402
PARAMETER
DC Operating Voltage Range
Input Voltage Range
MIN
4
V
SS
MAX
10.5
V
DD
MIN
4
V
SS
CDP6402C
MAX
6.5
V
DD
UNITS
V
V
Static Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
±10%,
Except as noted
CONDITIONS
CDP6402
V
O
(V)
I
DD
-
-
Output Low Drive
(Sink) Current
I
OL
0.4
0.5
Output High Drive
(Source) Current
I
OH
4.6
9.5
Output Voltage Low-
Level (Note 2)
V
OL
-
-
Output Voltage
High Level (Note 2)
V
OH
-
-
Input Low Voltage
V
IL
0.5, 4.5
0.5, 9.5
V
IN
(V)
0, 5
0,10
0,5
0,10
0, 5
0,10
0, 5
0, 10
0, 5
0, 10
-
-
V
DD
(V)
5
10
5
10
5
10
5
10
5
10
5
10
(NOTE 1)
TYP
0.01
1
4
7
-1.1
-2.6
0
0
5
10
-
-
LIMITS
CDP6402C
(NOTE 1)
TYP
0.02
-
2.4
-
-1.1
-
0
-
5
-
-
-
PARAMETER
Quiescent Device
Current
MIN
-
-
2
5
-0.55
-1.3
-
-
4.9
9.9
-
-
MAX
50
200
-
-
-
-
0.1
0.1
-
-
0.8
0.2 V
DD
MIN
-
-
1.2
-
-0.55
-
-
-
4.9
-
-
-
MAX
200
-
-
-
-
-
0.1
-
-
-
0.8
-
UNITS
µA
µA
mA
mA
mA
mA
V
V
V
V
V
V
5-76
CDP6402, CDP6402C
Static Electrical Specifications
at T
A
= -40
o
C to +85
o
C, V
DD
±10%,
Except as noted
(Continued)
CONDITIONS
CDP6402
V
O
(V)
V
IH
0.5, 4.5
0.5, 9.5
Input Leakage
Current
I
IN
Any
Input
V
IN
(V)
-
-
0,5
0,10
Three-State Output
Leakage Current
I
OUT
0, 5
0, 10
Operating Current
(Note 3)
I
DD1
-
-
Input Capacitance
Output Capacitance
NOTES:
1. Typical values are for T
A
= 25
o
C and nominal V
DD
2. I
OL
= I
OH
= 1µA.
3. Operating current is measured at 200kHz or V
DD
= 5V and 400kHz for V
DD
= 10V, with open outputs (worst-case frequencies for
CDP1802A system operating at maximum speed of 3.2MHz).
C
IN
C
OUT
-
-
0, 5
0,10
0, 5
0,10
-
-
V
DD
(V)
5
10
5
10
5
10
5
10
-
-
(NOTE 1)
TYP
-
-
±10
-4
±10
-4
±10
-4
±10
-4
1.5
10
5
10
LIMITS
CDP6402C
(NOTE 1)
TYP
-
-
-
-
±10
-4
-
1.5
-
5
10
PARAMETER
Input High Voltage
MIN
V
DD
-2
7
-
-
-
-
-
-
-
-
MAX
-
-
±1
±2
±1
±10
−
−
7.5
15
MIN
V
DD
-2
-
-
-
-
-
-
-
-
-
MAX
-
-
±1
-
±1
-
-
-
7.5
15
UNITS
V
V
µA
µA
µA
µA
mA
mA
pF
pF
5-77
CDP6402, CDP6402C
Description of Operation
Initialization and Controls
A positive pulse on the MASTER RESET (MR) input resets
the control, status, and receiver buffer registers, and sets the
serial output (TRO) High. Timing is generated from the clock
inputs RRC and TRC at a frequency equal to 16 times the
serial data bit rate. The RRC and TRC inputs may be driven
by a common clock, or may be driven independently by two
different clocks. The CONTROL REGISTER LOAD (CRL)
input is strobed to load control bits for PARITY INHIBIT (PI),
EVEN PARITY ENABLE (EPE), STOP BIT SELECTS (SBS),
and CHARACTER LENGTH SELECTS (CLS1 and CLS2).
These inputs may be hand wired to V
SS
or V
DD
with CRL to
V
DD
. When the initialization is completed, the UART is ready
for receiver and/or transmitter operations.
Transmitter Operation
The transmitter section accepts parallel data, formats it, and
transmits it in serial form (Figure 2) on the TRO terminal.
START
BIT
LSB
5 - 8 DATA BITS
1, 1-1/2 OR
2 STOP BITS
FE, PE
1/2 CLOCK
CYCLES
Receiver Operation
Data is received in serial form at the RRl input. When no
data is being received, RRI input must remain high. The data
is clocked through the RRC. The clock rate is 16 times the
data rate. Receiver timing is shown in Figure 4.
BEGINNING OF FIRST STOP BIT
RRI
RBRI-8, OE
DATA
8 1/2 TO 9 1/2
CLOCK CYCLES
DRR
DR
A
B
C
FIGURE 4. RECEIVER TIMING WAVEFORMS
MSB
†
PARITY
†
IF ENABLED
FIGURE 2. SERIAL DATA FORMAT
Transmitter timing is shown in Figure 3. (A) Data is loaded
into the transmitter buffer register from the inputs TBR1
through TBR8 by a logic low on the TBRL input. Valid data
must be present at least t
DT
prior to, and t
TD
following, the
rising edge of TBRL. If words less than 8-bits are used, only
the least significant bits are used. The character is right justi-
fied into the least significant bit, TBR1. (B) The rising edge of
TBRL clears TBRE. 1/2 to 11/2 cycles later, depending on
when the TBRL pulse occurs with respect to TRC, data is
transferred to the transmitter register and TRE is cleared.
TBRE is set to a logic High one cycle after that.
Output data is clocked by TRC. The clock rate is 16 times
the data rate. (C) A second pulse on TBRL loads data into
the transmitter buffer register. Data transfer to the transmitter
register is delayed until transmission of the current character
is complete. (D) Data is automatically transferred to the
transmitter register and transmission of that character
begins.
TBRL
(A) A low level on DRR clears the DR line. (B) During the first
stop bit data is transferred from the receiver register to the
RB Register. If the word is less than 8 bits, the unused most
significant bits will be a logic low. The output character is
right justified to the least significant bit RBR1. A logic high on
OE indicates overruns. An overrun occurs when DR has not
been cleared before the present character was transferred to
the RBR. (C) 1/2 clock cycle later DR is set to a logic high
and FE is evaluated. A logic high on FE indicates an invalid
stop bit was received. A logic high on PE indicates a parity
error.
Start Bit Detection
The receiver uses a 16X clock for timing (Figure 5). The start
bit could have occurred as much as one clock cycle before it
was detected, as indicated by the shaded portion. The cen-
ter of the start bit is defined as clock count 7 1/2. If the
receiver clock is a symmetrical square wave, the center of
the start bit will be located within
±1/2
clock cycle
±1/32
bit or
±3.125%.
The receiver begins searching for the next start bit
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