82V3255TFG8 datasheet, PDF - EEWORLD Datasheet

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82V3255TFG8: DescriptionTQFP-64, Reel; CategoryWireless rf/communication Telecom circuit; File Size1MB，173 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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TQFP-64, Reel

82V3255TFG8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	10 X 10 MM, 1.40 MM HEIGHT, GREEN, MO-136BJ, MS-026BCB, TQFP-64
Contacts	64
Manufacturer packaging code	PPG64
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.6 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	10 mm
Base Number Matches	1

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WAN PLL

IDT82V3280

Version 7

June 22, 2015

6024 Silver Creek Valley Road, San Jose, CA 95138

Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775

Printed in U.S.A.

Table of Contents

FEATURES .............................................................................................................................................................................. 9

HIGHLIGHTS.................................................................................................................................................................................................... 9

MAIN FEATURES ............................................................................................................................................................................................ 9

OTHER FEATURES ......................................................................................................................................................................................... 9

APPLICATIONS....................................................................................................................................................................... 9

DESCRIPTION....................................................................................................................................................................... 10

FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11

1 PIN ASSIGNMENT ........................................................................................................................................................... 12

2 PIN DESCRIPTION .......................................................................................................................................................... 13

3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 19

RESET ........................................................................................................................................................................................................... 19

MASTER CLOCK .......................................................................................................................................................................................... 19

INPUT CLOCKS & FRAME SYNC SIGNAL ................................................................................................................................................. 20

3.3.1 Input Clocks .................................................................................................................................................................................... 20

3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 20

3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 21

3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 23

3.5.1 LOS Monitoring .............................................................................................................................................................................. 23

3.5.2 Activity Monitoring ......................................................................................................................................................................... 23

3.5.3 Frequency Monitoring ................................................................................................................................................................... 24

3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 25

3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 25

3.6.2 Forced Selection ............................................................................................................................................................................ 26

3.6.3 Automatic Selection ....................................................................................................................................................................... 26

3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 27

3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 27

3.7.1.1 Fast Loss .......................................................................................................................................................................... 27

3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 27

3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 27

3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 27

3.7.2 Locking Status ............................................................................................................................................................................... 27

3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 28

3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 29

3.8.1 Input Clock Validity ........................................................................................................................................................................ 29

3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 29

3.8.2.1 Revertive Switch ............................................................................................................................................................... 29

3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 30

3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 30

3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 31

3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 31

3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 33

3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 34

3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 34

3.10.1.1 Free-Run Mode ................................................................................................................................................................ 34

3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 34

3.10.1.3 Locked Mode .................................................................................................................................................................... 34

3.1

3.2

3.3

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June 22, 2015

IDT82V3280

WAN PLL

3.11

3.12

3.13

3.14

3.15

3.16

3.17

4.1

5.1

5.2

5.3

5.4

5.5

3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 34

3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 34

3.10.1.5 Holdover Mode ................................................................................................................................................................. 34

3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 35

3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 35

3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 35

3.10.1.5.4 Manual ........................................................................................................................................................... 35

3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 35

3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 35

3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 35

3.10.2.1 Free-Run Mode ................................................................................................................................................................ 35

3.10.2.2 Locked Mode .................................................................................................................................................................... 35

3.10.2.3 Holdover Mode ................................................................................................................................................................. 35

T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 37

3.11.1 PFD Output Limit ............................................................................................................................................................................ 37

3.11.2 Frequency Offset Limit .................................................................................................................................................................. 37

3.11.3 PBO (T0 only) ................................................................................................................................................................................. 37

3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 37

3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 37

3.11.5.1 T0 Path ............................................................................................................................................................................. 37

3.11.5.2 T4 Path ............................................................................................................................................................................. 38

T0 / T4 APLL ................................................................................................................................................................................................. 39

OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 39

3.13.1 Output Clocks ................................................................................................................................................................................. 39

3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 42

MASTER / SLAVE CONFIGURATION ......................................................................................................................................................... 44

INTERRUPT SUMMARY ............................................................................................................................................................................... 45

T0 AND T4 SUMMARY ................................................................................................................................................................................. 45

POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 46

MASTER / SLAVE APPLICATION ............................................................................................................................................................... 47

4 TYPICAL APPLICATION ................................................................................................................................................. 47

5 MICROPROCESSOR INTERFACE .................................................................................................................................. 48

EPROM MODE .............................................................................................................................................................................................. 49

MULTIPLEXED MODE .................................................................................................................................................................................. 50

INTEL MODE ................................................................................................................................................................................................. 52

MOTOROLA MODE ...................................................................................................................................................................................... 54

SERIAL MODE .............................................................................................................................................................................................. 56

6 JTAG ................................................................................................................................................................................ 58

7 PROGRAMMING INFORMATION .................................................................................................................................... 59

7.1

7.2

REGISTER MAP ............................................................................................................................................................................................ 59

REGISTER DESCRIPTION ........................................................................................................................................................................... 65

7.2.1 Global Control Registers ............................................................................................................................................................... 65

7.2.2 Interrupt Registers ......................................................................................................................................................................... 74

7.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 79

7.2.4 Input Clock Quality Monitoring Configuration & Status Registers ......................................................................................... 102

7.2.5 T0 / T4 DPLL Input Clock Selection Registers ........................................................................................................................... 116

7.2.6 T0 / T4 DPLL State Machine Control Registers ......................................................................................................................... 120

7.2.7 T0 / T4 DPLL & APLL Configuration Registers .......................................................................................................................... 122

7.2.8 Output Configuration Registers .................................................................................................................................................. 136

7.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 146

7.2.10 Synchronization Configuration Registers ................................................................................................................................. 148

JUNCTION TEMPERATURE ...................................................................................................................................................................... 149

8 THERMAL MANAGEMENT ........................................................................................................................................... 149

8.1

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June 22, 2015

IDT82V3280

WAN PLL

9 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 151

9.1

9.2

9.3

8.2

8.3

8.4

EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 149

HEATSINK EVALUATION .......................................................................................................................................................................... 149

TQFP EPAD THERMAL RELEASE PATH ................................................................................................................................................. 150

9.4

9.5

9.6

9.7

ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 151

RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 151

I/O SPECIFICATIONS ................................................................................................................................................................................. 152

9.3.1 AMI Input / Output Port ................................................................................................................................................................ 152

9.3.1.1 Structure ......................................................................................................................................................................... 152

9.3.1.2 I/O Level ......................................................................................................................................................................... 152

9.3.1.3 Over-Voltage Protection ................................................................................................................................................. 154

9.3.2 CMOS Input / Output Port ............................................................................................................................................................ 154

9.3.3 PECL / LVDS Input / Output Port ................................................................................................................................................ 155

9.3.3.1 PECL Input / Output Port ................................................................................................................................................ 155

9.3.3.2 LVDS Input / Output Port ................................................................................................................................................ 157

9.3.3.3 Single-Ended Input for Differential Input ........................................................................................................................ 158

JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 159

OUTPUT WANDER GENERATION ............................................................................................................................................................ 162

INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 163

OUTPUT CLOCK TIMING ........................................................................................................................................................................... 164

PACKAGE DIMENSIONS.................................................................................................................................................... 169

ORDERING INFORMATION................................................................................................................................................ 172

Table of Contents

June 22, 2015

82V3255TFG8 Related Products

	82V3255TFG8	82V3255TFG	82V3255EDG	82V3255TF
Description	TQFP-64, Reel	TQFP-64, Tray	TQFP-64, Tray	TQFP-64, Tray
Brand Name	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free	Lead free	Contains lead
Is it Rohs certified?	conform to	conform to	conform to	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	TQFP	TQFP	TQFP
package instruction	10 X 10 MM, 1.40 MM HEIGHT, GREEN, MO-136BJ, MS-026BCB, TQFP-64	10 X 10 MM, 1.40 MM HEIGHT, GREEN, MO-136BJ, MS-026BCB, TQFP-64	10 X 10 MM, 1 MM HEIGHT, GREEN, MS-026ACD, TQFP-64	10 X 10 MM, 1.40 MM HEIGHT, MO-136BJ, MS-026BCB, TQFP-64
Contacts	64	64	64	64
Manufacturer packaging code	PPG64	PPG64	EDG64	PP64
Reach Compliance Code	compliant	compliant	compliant	not_compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
JESD-30 code	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64
JESD-609 code	e3	e3	e3	e0
length	10 mm	10 mm	10 mm	10 mm
Humidity sensitivity level	3	3	3	3
Number of functions	1	1	1	1
Number of terminals	64	64	64	64
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	HTFQFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260	260	240
Maximum seat height	1.6 mm	1.6 mm	1.2 mm	1.6 mm
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	MATTE TIN	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	NOT SPECIFIED	20
width	10 mm	10 mm	10 mm	10 mm
Base Number Matches	1	1	1	1
Certification status	-	Not Qualified	Not Qualified	Not Qualified

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