80C86_06 datasheet, PDF - EEWORLD Datasheet

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80C86_06: Description16-BIT, 8 MHz, MICROPROCESSOR, PDIP40; Categorysemiconductor The embedded processor and controller; File Size575KB，37 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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80C86_06 Overview

16-BIT, 8 MHz, MICROPROCESSOR, PDIP40

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80C86

CMOS 16-Bit Microprocessor

Description

The Intersil 80C86 high performance 16-bit CMOS CPU is

manufactured using a self-aligned silicon gate CMOS pro-

cess (Scaled SAJI IV). Two modes of operation, minimum for

small systems and maximum for larger applications such as

multiprocessing, allow user configuration to achieve the

highest performance level. Full TTL compatibility (with the

exception of CLOCK) and industry standard operation allow

use of existing NMOS 8086 hardware and software designs.

August 22, 2006

Features

• Compatible with NMOS 8086

• Completely Static CMOS Design

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8MHz (80C86-2)

• Low Power Operation

- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500μA Max

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ

• 1MByte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary, or Decimal

- Multiply and Divide

• Wide Operating Temperature Range

- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

- M80C86 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Ordering Information

TEMP.

RANGE

(°C)

0 to +70

CERDIP

SMD#

-55 to +125

PART

MARKING

CP80C86-2

CP80C86-2Z

MD80C86-2/B

8405202QA

PKG.

NO.

E40.6

F40.6

PACKAGE

PDIP

8MHz

CP80C86-2

CP80C86-2Z

MD80C86-2/B

8405202QA

Pinouts

80C86 (DIP)

TOP VIEW

AD12

AD11

GND

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMI

INTR

CLK

GND

MAX

40 V

39 AD15

38 A16/S3

AD11

37 A17/S4

36 A18/S5

35 A19/S6

34 BHE/S7

33 MN/MX

32 RD

31 RQ/GT0

30 RQ/GT1

29 LOCK

28 S2

27 S1

26 S0

25 QS0

24 QS1

23 TEST

22 READY

21 RESET

READY

RESET

TEST

INTR

GND

CLK

QS1

QS0

NMI

(HOLD)

(HLDA)

(WR)

(M/IO)

(DT/R))

(DEN)

(ALE)

(INTA)

READY

RESET

TEST

INTR

INTA

GND

CLK

ALE

NMI

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

MIN MODE

80C86

18 19 20 21 22 23 24 25 26 27 28

80C86 (PLCC, CLCC)

TOP VIEW

A16/S3

A17/S4

A18/S5

A17/S4

A18/S5

AD13

AD14

MAX MODE

80C86

AD12

AD13

AD14

1 44 43 42 41 40

AD15

GND

AD15

GND

(MIN)

A19/S6

BHE/S7

MN/MX

RQ/GT0

RQ/GT1

LOCK

BHE/S7

MN/MX

HOLD

HLDA

M/IO

DT/R

DEN

MIN MODE

80C86

MAX MODE

80C86

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

FN2957.2

141

80C86

Pin Description

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

NUMBER

2-16, 39

SYMBOL

AD15-AD0

TYPE

I/O

DESCRIPTION

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and

data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-

D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory

or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-

dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-

ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”

or “grant sequence”.

ADDRESS/STATUS: During T1, these are the four most significant address lines for memory op-

erations. During I/O operations these lines are LOW. During memory and I/O operations, status

information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of

the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3

are encoded as shown.

This information indicates which segment register is presently being used for data accessing.

These lines are held at high impedance to the last valid logic level during local bus “hold ac-

knowledge” or “grant sequence”.

CHARACTERISTICS

Alternate Data

Stack

Code or None

Data

A19/S6

A18/S5

A17/S4

A16/S3

35-38

BHE/S7

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to

enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices

tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE

is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-

ferred on the high portion of the bus. The S7 status information is available during T2, T3 and

T4. The signal is active LOW, and is held at high impedance to the last valid logic level during

interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during

T1 for the first interrupt acknowledge cycle.

BHE

CHARACTERISTICS

Whole Word

Upper Byte From/to Odd Address

Lower Byte From/to Even address

None

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-

pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on

the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-

teed to remain HIGH in T2 until the 80C86 local bus has floated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-

quence”.

READY

READY: is the acknowledgment from the addressed memory or I/O device that will complete the

data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gen-

erator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.

Correct operation is not guaranteed if the Setup and Hold Times are not met.

143

80C86

Pin Description

(Continued)

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

NUMBER

SYMBOL

INTR

TYPE

DESCRIPTION

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle

of each instruction to determine if the processor should enter into an interrupt acknowledge op-

eration. A subroutine is vectored to via an interrupt vector lookup table located in system mem-

ory. It can be internally masked by software resetting the interrupt enable bit.

lNTR is internally synchronized. This signal is active HIGH.

TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each

clock cycle on the leading edge of CLK.

NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A

subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is

not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the

end of the current instruction. This input is internally synchronized.

RESET: causes the processor to immediately terminate its present activity. The signal must tran-

sition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution,

as described in the Instruction Set description, when RESET returns LOW. RESET is internally

synchronized.

CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a

33% duty cycle to provide optimized internal timing.

VCC: +5V power supply pin. A 0.1μF capacitor between pins 20 and 40 is recommended for de-

coupling.

GND: Ground. Note: both must be connected. A 0.1μF capacitor between pins 1 and 20 is rec-

ommended for decoupling.

TEST

NMI

RESET

CLK

VCC

GND

1, 20

MN/MX

MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are

discussed in the following sections.

Minimum Mode System

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V

). Only the pin functions which are unique to

minimum mode are described; all other pin functions are as described below.

NUMBER

SYMBOL

M/IO

TYPE

DESCRIPTION

STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-

ory access from an I/O access. M/lO becomes valid in the T4 preceding a bus cycle and remains

valid until the final T4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic

one during local bus “hold acknowledge”.

WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending

on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active

LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is

active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never

floated.

ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the

82C82/82C83 address latch. It is a HIGH pulse active during clock LOW of T1 of any bus cycle.

Note that ALE is never floated.

INTA

ALE

144

80C86

Minimum Mode System

(Continued)

The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V

). Only the pin functions which are unique to

minimum mode are described; all other pin functions are as described below.

NUMBER

SYMBOL

DT/R

TYPE

DESCRIPTION

DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus

transceiver. It is used to control the direction of data flow through the transceiver. Logically,

DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,

R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.

DATA ENABLE: provided as an output enable for a bus transceiver in a minimum system which

uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cy-

cles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for

a write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high

impedance logic one during local bus “hold acknowledge”.

HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged,

HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge”

(HLDA) in the middle of a T4 or TI clock cycle. Simultaneously with the issuance of HLDA, the

processor will float the local bus and control lines. After HOLD is detected as being LOW, the

processor will lower HLDA, and when the processor needs to run another cycle, it will again drive

the local bus and control lines.

HOLD is not an asynchronous input. External synchronization should be provided if the system

cannot otherwise guarantee the setup time.

DEN

HOLD

HLDA

31, 30

Maximum Mode System

The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are

unique to maximum mode are described below.

NUMBER

SYMBOL

TYPE

DESCRIPTION

STATUS: is active during T4, T1 and T2 and is returned to the passive state (1, 1, 1) during T3

or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate

all memory and I/O access control signals. Any change by S2, S1 or S0 during T4 is used to

indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to

indicate the end of a bus cycle.

These signals are held at a high impedance logic one state during “grant sequence”.

CHARACTERISTICS

Interrupt Acknowledge

Read I/O Port

Write I/O Port

Halt

Code Access

Read Memory

Write Memory

Passive

145

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