BACK
IR3Y48A1
IR3Y48A1
DESCRIPTION
CCD Signal Process & Digital Interface IC
PIN CONNECTIONS
48-PIN QFP
TOP VIEW
The IR3Y48A1 is a CMOS single-chip signal
processing IC for CCD area sensors which includes
correlated double sampling circuit (CDS), clamp
circuit, programmable gain amplifier (PGA),
reference voltage generator, black level detection
circuit, 18 MHz 10-bit analog-to-digital converter
(ADC), timing generator for internally required
pulses, and serial interface for internal function
control and PGA gain control.
48 47 46 45 44 43 42 41 40 39 38 37
NC 1
AV
DD4
2
NC 3
V
RN
4
V
RP
5
AV
DD2
6
AV
DD2
7
AV
SS2
8
AV
SS2
9
V
COM
10
CCDIN 11
REFIN 12
13 14 15 16 17 18 19 20 21 22 23 24
CLPCAP
ADIN
OBCAP
MONOUT
NC
AISET
AV
DD1
AV
SS1
NC
ADCK
SHR
SHD
36 OUTCK
35 RESETN
34 AV
DD3
33 AV
SS3
32 STBYN
31 CSN
30 SDATA
29 SCK
28 OBP
27 CCDCLP
26 BLK
25 ADCLP
FEATURES
• Low power consumption : 80 mW (TYP.)
• Wide gain range : –1.94 to 36 dB
(Gain step : 0.047 dB/step)
• High speed sample-and-hold circuits :
pulse width 11 ns (MIN.)
• Independent CDS and PGA gain control
– CDS : –1.94/0/6/12 dB
– PGA : 0 to 24 dB
• Black level canceler
– Settling target : 16 to 127 LSB
• Capable of independent input of ADC conversion
clock and data output clock
• Power down mode : less than 1 mW
• Built-in serial interface
• 10-bit ADC operating up to 18 MHz
– DNL : ±0.6 LSB (TYP.)
• Maximum input level of CCD signals : 1.1 Vp-p
• Accepts a direct signal input to ADC or PGA
(input level : 1.0 Vp-p (TYP.))
• Single 2.7 to 3.6 V power supply
• Package :
48-pin QFP
*
(P-QFP048-0707) 0.5 mm pin-pitch
* Contact SHARP in order to obtain the details of
package dimensions of the IR3Y48A1.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
DO
9
DO
8
DO
7
DO
6
DO
5
DV
DD
DV
SS
DO
4
DO
3
DO
2
DO
1
DO
0
(P-QFP048-0707)
IR3Y48A1
PIN DESCRIPTION
PIN NO. SYMBOL
1 NC
2
3
AV
DD4
NC
I/O
–
–
–
V
DD
EQUIVALENT CIRCUIT
DESCRIPTION
No connection.
Supply of 2.7 to 3.6 V analog power.
No connection.
ADC internal negative reference
voltage.
(Connect to AV
SS
via 0.1 µF.)
ADC internal positive reference
4
V
RN
O
5
V
RP
O
◊
GND
voltage.
(Connect to AV
SS
via 0.1 µF.)
Supply of 2.7 to 3.6 V analog power.
Supply of 2.7 to 3.6 V analog power.
An analog grounding pin.
An analog grounding pin.
6
7
8
9
AV
DD2
AV
DD2
AV
SS2
AV
SS2
–
–
–
–
V
DD
ADC internal common reference
voltage.
(Connect to AV
SS
via 0.1 µF.)
10
V
COM
O
10
◊
GND
CDS circuit data input.
V
DD
11
CCDIN
I
CDS circuit reference input.
12
REFIN
I
◊
GND
13
14
15
16
CLPCAP
ADIN
OBCAP
MONOUT
O
I
O
◊
Clamp level output.
V
DD
(Connect to AV
SS
via 0.1 µF.)
ADIN signal input.
Black level integration voltage.
(Connect to AV
SS
via 0.1 µF.)
O
GND
Monitor output of CDS or PGA.
◊ Internal FET gate
3
IR3Y48A1
PIN NO. SYMBOL
17 NC
I/O
–
V
DD
EQUIVALENT CIRCUIT
DESCRIPTION
No connection.
Internal analog circuit bias current
input.
(Connect to AV
SS
via 4.7 k$.)
18
AISET
*
I
18
◊
GND
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
AV
DD1
AV
SS1
NC
ADCK
SHR
SHD
ADCLP
BLK
CCDCLP
OBP
SCK
SDATA
CSN
STBYN
AV
SS3
AV
DD3
–
–
–
I
I
I
I
I
I
I
I
I
I
I
–
–
V
DD
GND
Supply of 2.7 to 3.6 V analog power.
An analog grounding pin.
No connection.
ADC sampling clock input.
Reference sampling pulse input.
V
DD
Data sampling pulse input.
Pulse input for ADIN clamp and
black calibration control.
Blanking pulse input.
Clamp control input.
Black level period pulse input.
Serial port clock input.
Serial port data input.
Serial port chip selection (active at low).
Power down control (power down at low).
An analog grounding pin.
Supply of 2.7 to 3.6 V analog power.
Reset signal input (reset at low).
35
RESETN
I
Clock input for ADC output.
36
OUTCK
I
GND
* High-Z at power down ◊ Internal FET gate
4
IR3Y48A1
PIN NO. SYMBOL
37
38
39
40
41
42
43
44
45
46
47
48
DO
0*
DO
1*
DO
2*
DO
3*
DO
4*
DV
SS
DV
DD
DO
5*
DO
6*
DO
7*
DO
8*
DO
9*
I/O
O
V
DD
EQUIVALENT CIRCUIT
DESCRIPTION
ADC digital output (3 state) (LSB).
ADC digital output (3 state).
ADC digital output (3 state).
ADC digital output (3 state).
GND
O
O
O
O
–
–
O
V
DD
ADC digital output (3 state).
A digital grounding pin.
Supply of 2.7 to 3.6 V digital power.
ADC digital output (3 state).
ADC digital output (3 state).
ADC digital output (3 state).
ADC digital output (3 state).
GND
O
O
O
O
ADC digital output (3 state) (MSB).
* High-Z at power down
NOTE :
NC pins are not connected internally, but recommended to be connected to AV
SS
.
5
Recruitment
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