EEWORLDEEWORLDEEWORLD

Part Number

Search

2SK1959-AZ

Description
Power Field-Effect Transistor, 2A I(D), 16V, 0.5ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET
CategoryDiscrete semiconductor    The transistor   
File Size60KB,6 Pages
ManufacturerNEC Electronics
Download Datasheet Parametric Compare View All

2SK1959-AZ Overview

Power Field-Effect Transistor, 2A I(D), 16V, 0.5ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET

2SK1959-AZ Parametric

Parameter NameAttribute value
MakerNEC Electronics
package instructionSMALL OUTLINE, R-PSSO-F3
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresGATE PROTECTED
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage16 V
Maximum drain current (ID)2 A
Maximum drain-source on-resistance0.5 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PSSO-F3
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum pulsed drain current (IDM)4 A
Certification statusNot Qualified
surface mountYES
Terminal formFLAT
Terminal locationSINGLE
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SK1959
N-CHANNEL MOS FET FOR HIGH-SPEED SWITCHING
The 2SK1959 is an N-channel vertical MOS FET. Because
it can be driven by a voltage as low as 1.5 V and it is not
necessary to consider a drive current, this FET is ideal as an
actuator for low-current portable systems such as headphone
stereos and video cameras.
PACKAGE DIMENSIONS (in mm)
4.5 ±0.1
1.6 ±0.2
1.5 ±0.1
• Gate can be driven by 1.5 V
• Low ON resistance
R
DS(on)
= 3.2
MAX.
R
DS(on)
= 0.5
MAX.
@ V
GS
= 1.5 V, I
D
= 50 mA
@ V
GS
= 4.0 V, I
D
= 1.0 A
0.8 MIN.
FEATURES
S
0.42 ±0.06
D
G
0.42 ±0.06
1.5 0.47
±0.06
3.0
0.41
+0.03
–0.05
Marking: NQ
EQUIVALENT CURCUIT
Drain (D)
Gate (G)
Gate
protection
diode
Source (S)
Internal
diode
PIN CONNECTIONS
S: Source
D: Drain
G: Gate
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 ˚C)
PARAMETER
Drain to Source Voltage
Gate to Source Voltage
Drain Current (DC)
Drain Current (Pulse)
Total Power Dissipation
Channel Temperature
Storage Temperature
SYMBOL
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
T
ch
T
stg
PW
10 ms, duty cycle
50 %
16 cm
2
×
0.7 mm ceramic substrate used
V
GS
= 0
V
DS
= 0
TEST CONDITIONS
RATING
16
±7.0
±2.0
±4.0
2.0
150
–55 to +150
UNIT
V
V
A
A
W
˚C
˚C
Document No. D11222EJ2V0DS00 (2nd edition)
Date Published June 1996 P
Printed in Japan
4.0 ±0.25
2.5 ±0.1
©
1996

2SK1959-AZ Related Products

2SK1959-AZ
Description Power Field-Effect Transistor, 2A I(D), 16V, 0.5ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET
Maker NEC Electronics
package instruction SMALL OUTLINE, R-PSSO-F3
Reach Compliance Code unknown
ECCN code EAR99
Other features GATE PROTECTED
Shell connection DRAIN
Configuration SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 16 V
Maximum drain current (ID) 2 A
Maximum drain-source on-resistance 0.5 Ω
FET technology METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PSSO-F3
Number of components 1
Number of terminals 3
Operating mode ENHANCEMENT MODE
Package body material PLASTIC/EPOXY
Package shape RECTANGULAR
Package form SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED
Polarity/channel type N-CHANNEL
Maximum pulsed drain current (IDM) 4 A
Certification status Not Qualified
surface mount YES
Terminal form FLAT
Terminal location SINGLE
Maximum time at peak reflow temperature NOT SPECIFIED
transistor applications SWITCHING
Transistor component materials SILICON
Base Number Matches 1
Newbie asks about PB5 simulator
I have just started my career in wince and plan to run an emulator on PB5 for fun. I thought the configuration would be very simple, but I was confused again. The problems are as follows: 1. Compilati...
huanque1 Embedded System
Official notice on the online release of the 2009 national competition questions
[i=s]This post was last edited by paulhyde on 2014-9-15 09:17[/i][table=90%][tr][td][/td][/tr][tr][td][/td][/tr][tr][td][align=center][b][font=华文中宋][size=14pt]Official Notice on the Online Posting of ...
T待鸿 Electronics Design Contest
CPLD and 51 single-chip computer bus interface program
timescale 1ns/1ns module IO_KZ(Data,P27,WR,RD,ALE,CLR,OUTKEY,OUT30,CS,CS1,LEDCS,OC); inout [7:0]Data; input WR; input P27; input RD; input ALE; input CLR; input OC; input [4:0]OUTKEY; output [59:0]OUT...
aimyself FPGA/CPLD
30 practical tips for reducing noise and electromagnetic interference!
[size=4] Electronic devices are becoming more and more sensitive, which requires the devices to have stronger anti-interference capabilities. Therefore, PCB design has become more difficult. How to im...
fish001 Energy Infrastructure?
How to set up a shortcut on the wince desktop?
I want to delete all the shortcuts on the desktop and replace them with my own logo. . . . But I found that I don’t know how to delete ordinary shortcuts. After deleting them, they reappear when I res...
sucuiqin Embedded System
Design and Analysis of Bidirectional DC-DC Converters
This article mainly introduces the design and analysis of a new bidirectional DC-DC converter. This new topology and its control strategy completely solve the voltage spike problem existing in traditi...
buildele Power technology

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1031  2823  2674  12  1815  21  57  54  1  37 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号