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PDM31564SA12TITY

Description
Standard SRAM, 256KX16, 12ns, CMOS, PDSO44
Categorystorage    storage   
File Size365KB,9 Pages
ManufacturerParadigm Technology Inc
Download Datasheet Parametric View All

PDM31564SA12TITY Overview

Standard SRAM, 256KX16, 12ns, CMOS, PDSO44

PDM31564SA12TITY Parametric

Parameter NameAttribute value
MakerParadigm Technology Inc
package instruction,
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time12 ns
JESD-30 codeR-PDSO-G44
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals44
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX16
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal locationDUAL
Base Number Matches1
PRELIMINARY
PDM31564
PDM31564
256K x 16 CMOS
3.3V Static RAM
Features
n
Description
The PDM31564 is a high-performance CMOS static
RAM organized as 262,144 x 16 bits. The PDM31564
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
The PDM31564 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
The PDM31564 is available in a 44-pin 400-mil plas-
tic SOJ and a plastic TSOP package for high-density
surface assembly and is suitable for use in high-
speed applications requiring high-speed storage.
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6
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High-speed access times
- Com’l: 8, 10, 12, 15, and 20 ns
- Ind: 12, 15, and 20 ns
Low power operation (typical)
- PDM31564SA
Active: 300 mW
Standby: 25mW
High-density 256K x 16 architecture
3.3V (±0.3V) power supply
Fully static operation
TTL-compatible inputs and outputs
Output buffer controls: OE
Data byte controls: LB, UB
Packages:
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
Functional Block Diagram
Row Address
Buffer
Row Decoder
Vcc
Vss
7
Memory
Cell
Array
256 x
x
128 x 32
512 256 x
A8 - A0
A7-A0
8
9
10
11
I/O15-I/O0
Data
Input/
Output
Buffer
Sense Amp
Column
Decoder
WE
OE
UB
LB
CE
Control
Logic
Clock
Generator
Column
Address
Buffer
12
A17 - A9
A15-A8
Rev. 1.2 - 3/31/98
1
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