CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
SUPPLY
=
5V,
A
V
= +1, R
F
= 510, R
L
= 100, Unless Otherwise Specified
TEST
CONDITIONS
TEST
LEVEL
(Note 2)
TEMP.
(°C)
PARAMETER
INPUT CHARACTERISTICS
Input Offset Voltage (Note 3)
MIN
TYP
MAX
UNITS
A
A
+25
Full
Full
+25
Full
+25
Full
+25
Full
Full
+25
Full
+25
Full
Full
+25
Full
+25
Full
+25
+25
+25
Full
+25
+25
+25
-
-
-
40
38
45
42
-
-
-
-
-
-
-
-
-
-
-
-
25
-
-
2.5
-
-
-
2
-
10
46
-
50
-
25
-
40
20
-
12
-
40
1
-
6
-
50
20
2
3.0
4
18
21
6
10
-
-
-
-
-
40
65
-
40
50
50
60
-
7
10
15
27
-
30
-
-
-
-
-
mV
mV
µV/°C
dB
dB
dB
dB
µA
µA
nA/°C
µA/V
µA/V
µA
µA
nA/°C
µA/V
µA/V
µA/V
µA/V
k
pF
V
nV/Hz
pA/Hz
pA/Hz
Input Offset Voltage Drift
V
IO
CMRR
V
CM
=
2V
C
A
A
V
IO
PSRR
V
S
=
1.25V
A
A
Non-Inverting Input Bias Current
(Note 3)
+I
BIAS
Drift
+I
BIAS
CMS
+IN = 0V
A
A
C
V
CM
=
2V
A
A
Inverting Input Bias Current (Note 3)
-IN = 0V
A
A
-I
BIAS
Drift
-I
BIAS
CMS
V
CM
=
2V
C
A
A
-I
BIAS
PSS
V
S
=
1.25V
A
A
Non-Inverting Input Resistance
Inverting Input Resistance
Input Capacitance (Either Input)
Input Common Mode Range
Input Noise Voltage (Note 3)
+Input Noise Current (Note 3)
-Input Noise Current (Note 3)
TRANSFER CHARACTERISTICS
100kHz
100kHz
100kHz
A
C
B
C
B
B
B
A
V
= +2, Unless Otherwise Specified
B
+25
-
300
-
k
Open Loop Transimpedance (Note 3)
FN3369 Rev 5.00
April 25, 2013
Page 2 of 13
HFA1130
Electrical Specifications
V
SUPPLY
=
5V,
A
V
= +1, R
F
= 510, R
L
= 100, Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
V
OUT
= 0.2V
P-P
,
A
V
= +1
V
OUT
= 0.2V
P-P
,
A
V
= +2, R
F
= 360
4V
P-P
, A
V
= -1
To 100MHz
To 50MHz
To 30MHz
DC to 100MHz
NTSC, R
L
= 75
NTSC, R
L
= 75
TEST
LEVEL
(Note 2)
B
B
B
B
B
B
B
B
B
A
A
V
= +2, Unless Otherwise Specified
A
V
= -1
A
A
Output Current
R
L
= 50, A
V
= -1
A
A
DC Closed Loop Output Impedance
(Note 3)
2nd Harmonic Distortion (Note 3)
3rd Harmonic Distortion (Note 3)
3rd Order Intercept (Note 3)
1dB Compression
30MHz, V
OUT
= 2V
P-P
30MHz, V
OUT
= 2V
P-P
100MHz
100MHz
B
B
B
B
B
+25
Full
+25,
+85
-40
+25
+25
+25
+25
+25
3.0
2.5
50
35
-
-
-
20
15
3.3
3.0
60
50
0.07
-56
-80
30
20
-
-
-
-
-
-
-
-
-
V
V
mA
mA
dBc
dBc
dBm
dBm
TEMP.
(°C)
+25
+25
Full
+25
+25
+25
+25
+25
+25
Full
PARAMETER
-3dB Bandwidth (Note 3)
-3dB Bandwidth
Full Power Bandwidth
Gain Flatness (Note 3)
Gain Flatness
Gain Flatness
Linear Phase Deviation (Note 3)
Differential Gain
Differential Phase
Minimum Stable Gain
OUTPUT CHARACTERISTICS
Output Voltage (Note 3)
MIN
530
-
-
-
-
-
-
-
-
1
TYP
850
670
300
0.14
0.04
0.01
0.6
0.03
0.05
-
MAX
-
-
-
-
-
-
-
-
-
-
UNITS
MHz
MHz
MHz
dB
dB
dB
°
%
°
V/V
TRANSIENT RESPONSE
A
V
= +2, Unless Otherwise Specified
Rise Time
Overshoot (Note 3)
Slew Rate
V
OUT
= 2.0V Step
V
OUT
= 2.0V Step
A
V
= +1,
V
OUT
= 5V
P-P
A
V
= +2,
V
OUT
= 5V
P-P
0.1% Settling Time (Note 3)
0.2% Settling Time (Note 3)
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range
Supply Current (Note 3)
B
A
A
LIMITING CHARACTERISTICS
Clamp Accuracy
Clamped Overshoot
Full
+25
Full
4.5
-
-
-
21
-
5.5
26
33
V
mA
mA
V
OUT
= 2V to 0V
V
OUT
= 2V to 0V
B
B
B
B
B
B
+25
+25
+25
+25
+25
+25
-
-
-
1850
-
-
900
10
1400
2300
11
7
-
-
-
-
-
-
ps
%
V/µs
V/µs
ns
ns
A
V
= +2, V
H
= +1V, V
L
= -1V, Unless Otherwise Specified
V
IN
=
2V,
A
V
= -1
V
IN
=
1V,
Input t
R
/t
F
= 2ns
A
B
+25
+25
-
-
60
4
125
-
mV
%
FN3369 Rev 5.00
April 25, 2013
Page 3 of 13
HFA1130
Electrical Specifications
V
SUPPLY
=
5V,
A
V
= +1, R
F
= 510, R
L
= 100, Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
V
IN
=
1V
TEST
LEVEL
(Note 2)
B
B
B
A
V
H
or V
L
= 100mV
P-P
B
TEMP.
(°C)
+25
+25
+25
+25
+25
PARAMETER
Overdrive Recovery Time
Negative Clamp Range
Positive Clamp Range
Clamp Input Bias Current
Clamp Input Bandwidth
NOTES:
MIN
-
-
-
-
-
TYP
0.75
-5.0 to +2.0
-2.0 to +5.0
50
500
MAX
1.5
-
-
200
-
UNITS
ns
V
V
µA
MHz
2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
3. See Typical Performance Curves for more information.
Application Information
Optimum Feedback Resistor (R
F
)
The enclosed plots of inverting and non-inverting frequency
response detail the performance of the HFA1130 in various
gains. Although the bandwidth dependency on A
CL
isn’t as
severe as that of a voltage feedback amplifier, there is an
appreciable decrease in bandwidth at higher gains. This
decrease can be minimized by taking advantage of the current
feedback amplifier’s unique relationship between bandwidth
and R
F
. All current feedback amplifiers require a feedback
resistor, even for unity gain applications, and the R
F
, in
conjunction with the internal compensation capacitor, sets the
dominant pole of the frequency response. Thus, the
amplifier’s bandwidth is inversely proportional to R
F
. The
HFA1130 design is optimized for a 510 R
F
, at a gain of +1.
Decreasing R
F
in a unity gain application decreases stability,
resulting in excessive peaking and overshoot (Note:
Capacitive feedback causes the same problems due to the
feedback impedance decrease at higher frequencies). At
higher gains the amplifier is more stable, so R
F
can be
decreased in a trade-off of stability for bandwidth. The table
below lists recommended R
F
values for various gains, and the
expected bandwidth.
A
CL
+1
-1
+2
+5
+10
+19
R
F
()
510
430
360
150
180
270
BW (MHz)
850
580
670
520
240
125
output above V
H
, or below V
L
, the clamp circuitry limits the
output voltage at V
H
or V
L
( the clamp accuracy),
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Clamp Circuitry
Figure 1 shows a simplified schematic of the HFA1130 input
stage, and the high clamp (V
H
) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (Q
X1
- Q
X2
)
between the positive and negative inputs. This buffer forces -IN
to track +IN, and sets up a slewing current of (V
-IN
- V
OUT
)/R
F
.
This current is mirrored onto the high impedance node (Z) by
Q
X3
-Q
X4
, where it is converted to a voltage and fed to the output
via another unity gain buffer. If no clamping is utilized, the high
impedance node may swing within the limits defined by Q
P4
and
Q
N4
. Note that when the output reaches it’s quiescent value, the
current flowing through -IN is reduced to only that small current
(-I
BIAS
) required to keep the output at the final voltage.
V+
Q
P3
Q
P4
50K
(30K
FOR V
L
)
+1
V
H
Q
P2
Q
N5
Q
N6
Q
P6
Q
N4
Q
P5
200
Q
N2
Q
P1
+IN
V-
V+
Q
N1
I
CLAMP
Z
R
1
Clamp Operation
General
The HFA1130 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the V
H
and V
L
terminals (pins 8 and
5) of the amplifier. V
H
sets the upper output limit, while V
L
sets the lower clamp level. If the amplifier tries to drive the
Q
N3
V-
-IN
R
F
(EXTERNAL)
V
OUT
FIGURE 1. HFA1130 SIMPLIFIED V
H
CLAMP CIRCUITRY
FN3369 Rev 5.00
April 25, 2013
Page 4 of 13
HFA1130
Tracing the path from V
H
to Z illustrates the effect of the
clamp voltage on the high impedance node. V
H
decreases
by 2V
BE
(Q
N6
and Q
P6
) to set up the base voltage on Q
P5
.
Q
P5
begins to conduct whenever the high impedance node
reaches a voltage equal to Q
P5
’s base + 2V
BE
(Q
P5
and
Q
N5
). Thus, Q
P5
clamps node Z whenever Z reaches V
H
.
R
1
provides a pull-up network to ensure functionality with the
clamp inputs floating. A similar description applies to the
symmetrical low clamp circuitry controlled by V
L
.
When the output is clamped, the negative input continues to
source a slewing current (I
CLAMP
) in an attempt to force the
output to the quiescent voltage defined by the input. Q
P5
must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as (V
-IN
- V
OUT
)/R
F
. As
an example, a unity gain circuit with V
IN
= 2V, V
H
= 1V, and
R
F
= 510 would have I
CLAMP
= (2-1)/510 = 1.96mA.
Note that I
CC
will increase by I
CLAMP
when the output is
clamp limited.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (V
CLAMP
/A
VCL
) the amplifier will
return to linear operation. A time delay, known as the
Overdrive Recovery Time, is required for this resumption of
linear operation. The plots of “Unclamped Performance” and
“Clamped Performance” highlight the HFA1130’s
subnanosecond recovery time. The difference between the
unclamped and clamped propagation delays is the overdrive
recovery time. The appropriate propagation delays are 4.0ns
for the unclamped pulse, and 4.8ns for the clamped (2X
overdrive) pulse yielding an overdrive recovery time of
800ps. The measurement uses the 90% point of the output
transition to ensure that linear operation has resumed.
Note: The propagation delay illustrated is dominated by the
fixturing. The delta shown is accurate, but the true HFA1130
propagation delay is 500ps.
Use of Die in Hybrid Applications
This amplifier is designed with compensation to negate the
package parasitics that typically lead to instabilities. As a
result, the use of die in hybrid applications results in
overcompensated performance due to lower parasitic
capacitances. Reducing R
F
below the recommended values
for packaged units will solve the problem. For A
V
= +2 the
recommended starting point is 300, while unity gain
applications should try 400.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to V
H
or V
L
. Offset errors, mostly due to V
BE
mismatches, necessitate a clamp accuracy parameter which is
found in the device specifications. Clamp accuracy is a function
of the clamping conditions. Referring again to Figure 1, it can
be seen that one component of clamp accuracy is the V
BE
mismatch between the Q
X6
transistors, and the Q
X5
transistors. If the transistors always ran at the same current
level there would be no V
BE
mismatch, and no contribution to
the inaccuracy. The Q
X6
transistors are biased at a constant
current, but as described earlier, the current through Q
X5
is
equivalent to I
CLAMP
. V
BE
increases as I
CLAMP
increases,
causing the clamped output voltage to increase as well. I
CLAMP
is a function of the overdrive level (V
-IN
-V
OUTCLAMPED
) and
R
F
, so clamp accuracy degrades as the overdrive increases, or
as R
F
decreases. As an example, the specified accuracy of
60mV
for a 2X overdrive with R
F
= 510 degrades to
220mV
for R
F
= 240 at the same overdrive, or to
250mV
for a 3X
overdrive with R
F
= 510.
Consideration must also be given to the fact that the clamp
voltages have an effect on amplifier linearity. The
“Nonlinearity Near Clamp Voltage” curve in the data sheet
illustrates the impact of several clamp levels on linearity.
PC Board Layout
The frequency performance of this amplifier depends a great
deal on the amount of care taken in designing the PC board.
The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10F) tantalum in parallel with a small value
chip (0.1F) capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Output capacitance, such as
that resulting from an improperly terminated transmission
line will degrade the frequency response of the amplifier and
may cause oscillations. In most cases, the oscillation can be
avoided by placing a resistor in series with the output.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input. The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and possible instability. To this end, it is
recommended that the ground plane be removed under
traces connected to pin 2, and connections to pin 2 should
be kept as short as possible.
An example of a good high frequency layout is the
Evaluation Board shown below.
Clamp Range
Unlike some competitor devices, both V
H
and V
L
have usable
ranges that cross 0V. While V
H
must be more positive than V
L
,
both may be positive or negative, within the range restrictions
indicated in the specifications. For example, the HFA1130 could
be limited to ECL output levels by setting V
H
= -0.8V and
V
L
= -1.8V. V
H
and V
L
may be connected to the same voltage
(GND for instance) but the result won’t be in a DC output
voltage from an AC input signal. A 150 - 200mV AC signal will
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Embedded System
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