This product has been retired and is not recommended for designs. For new designs, S29WS064K
supersedes Am29BDS640G. Please refer to the S29WS-K family data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes
only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
25903
Revision
C
Amendment
2
Issue Date
May 9, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29BDS640G
64 Megabit (4 M x 16-Bit), 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
This product has been retired and is not recommended for designs. For new designs, S29WS064K supersedes Am29BDS640G. Please refer to the S29WS-K family
data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.65 to
1.95 volt)
Manufactured on 0.17 µm process technology
Enhanced VersatileIO™ (V
IO
) Feature
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
— 1.8V and 3V compatible I/O signals
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
Sector Architecture
— Eight 8 Kword sectors and one hundred twenty-six
32 Kword sectors
— Banks A and D each contain four 8 Kword sectors and
thirty-one 32 Kword sectors; Banks B and C each
contain thirty-two 32 Kword sectors
— Eight 8 Kword boot sectors, four at the top of the
address range, and four at the bottom of the address
range
Minimum 1 million erase cycle guarantee per
sector
20-year data retention at 125°C
— Reliable operation for the life of the system
80-ball FBGA package
Power dissipation (typical values, C
L
= 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
Hardware Features
Sector Protection
— Software command sector locking
Handshaking feature available
— Provides host system with minimum possible latency
by monitoring RDY
Hardware reset input (RESET#)
— Hardware method to reset the device for reading
array data
WP# input
— Write protect (WP#) function protects sectors 0 and 1
(bottom boot), or sectors 132 and 133 (top boot),
regardless of sector protect status
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
V
IL
CMOS compatible inputs, CMOS compatible outputs
Low V
CC
write inhibit
Software Features
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC
42.4 standards
— Backwards compatible with Am29F and Am29LV
families
Data# Polling and toggle bits
— Provides a software method of detecting program
and erase operation completion
Erase Suspend/Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
PERFORMANCE CHARCTERISTICS
Read access times at 54/40 MHz (at 30 pF)
— Burst access times of 13.5/20 ns
— Asynchronous random access times of 70 ns
— Initial Synchronous access times as fast as 87.5/95 ns
Publication Number
25903
Revision
C
Amendment
2
Issue Date
May 9, 2006
D a t a
S h e e t
General Description
The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode
Flash memory device, organized as 4,194,304 words of 16 bits each. This device uses a
single V
CC
of 1.65 to 1.95 V to read, program, and erase the memory array. The device
supports Enhanced V
IO
to offer up to 3V compatible inputs and outputs. A 12.0-volt V
ID
may be used for faster program performance if desired. The device can also be pro-
grammed in standard EPROM programmers.
At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 87.5
ns at 30 pF. At 40 MHz, the device provides a burst access of 20 ns at 30 pF with a la-
tency of 95 ns at 30 pF. The device operates within the industrial temperature range of -
40°C to +85°C. The device is offered in the 80-ball FBGA package.
The Simultaneous Read/Write architecture provides
simultaneous operation
by divid-
ing the memory space into four banks. The device can improve overall system perfor-
mance by allowing a host system to program or erase in one bank, then immediately and
simultaneously read from another bank, with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is divided as shown in the following table:
Bank
A
B
C
D
Quantity
4
31
32
32
31
4
Size
8 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
8 Kwords
The Enhanced VersatileIO™ (V
IO
) control allows the host system to set the voltage levels
that the device generates at its data outputs and the voltages tolerated at its data inputs
to the same voltage level that is asserted on the V
IO
pin. This allows the device to operate
in 1.8 V and 3 V system environments as required.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Out-
put Enable (OE#) to control asynchronous read and write operations. For burst opera-
t i o n s , t h e d e v i c e a d d i t i o n a l l y r e q u i r e s Re a d y ( R DY ) , a n d C l o c k ( C L K ) . Th i s
implementation allows easy interface with minimal glue logic to a wide range of micropro-
cessors/microcontrollers for high performance read operations.
The burst read mode feature gives system designers flexibility in the interface to the de-
vice. The user can preset the burst length and wrap through the same memory space, or
read the flash array in continuous mode.
The clock polarity feature provides system designers a choice of active clock edges, either
rising or falling. The active clock edge initiates burst accesses and determines when data
will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-
supply Flash standard.
Commands are written to the command register using standard
microprocessor write timing. Register contents serve as inputs to an internal state-ma-
chine that controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out
of the device is similar to reading from other Flash or EPROM devices.
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold for
any period of time to read data from, or program data to, any sector that is not selected
for erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal
state machine to reading array data. The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the device, enabling the system microproces-
sor to read boot-up firmware from the Flash memory device.
The host system can detect whether a program or erase operation is complete by using
the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or
erase cycle has been completed, the device automatically returns to reading array data.
2
Am29BDS640G
25903C2 May 9, 2006
D a t a
S h e e t
The
sector erase architecture
allows memory sectors to be erased and reprogrammed
without affecting the data contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically in-
hibits write operations during power transitions. The device also offers two types of data
protection at the sector level. The
sector lock/unlock command sequence
disables or
re-enables both program and erase operations in any sector. When at V
IL
,
WP#
locks
sectors 0 and 1 (bottom boot device) or sectors 132 and 133 (top boot device).
The device offers two power-saving features. When addresses have been stable for a
specified amount of time, the device enters the
automatic sleep mode.
The system can
also place the device into the
standby mode.
Power consumption is greatly reduced in
both modes.
Spansion flash technology combines years of flash memory manufacturing experience to
produce the highest levels of quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The
京公网安备 11010802033920号
EEWORLD
