CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Full Scale Gain Error, FSE
Offset Drift Coefficient
Full Scale Output Current, I
FS
AV
EE
, DV
EE
= -4.94 to -5.46V, V
CC
= +4.75 to +5.25V, V
REF
= Internal T
A
= 25
o
C for All Typical Values
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
(Note 4) (“Best Fit” Straight Line)
(Note 4)
(Note 4)
(Notes 2, 4)
(Note 3)
-
-
-
-
-
-
(Note 3)
-1.25
-
0.75
0.5
20
1
-
20.48
-
-
1.5
1.0
75
10
0.05
-
0
Bits
LSB
LSB
A
%
A/
o
C
mA
V
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Throughput Rate
Output Voltage Full Scale Step
Settling Time, t
SETT
Full Scale
Single Glitch Area, GE (Peak)
Doublet Glitch Area, (Net)
Output Slew Rate
Output Rise Time
Output Fall Time
Differential Gain
Differential Phase
Spurious Free Dynamic Range to Nyquist
(Note 3)
(Note 5)
To
0.5
LSB Error Band R
L
= 50
(Note 3)
R
L
= 50(Note 3)
80
-
-
-
-
20
5
3
1,000
675
470
0.15
0.07
70
70
-
-
-
-
-
-
-
-
-
-
-
MSPS
ns
pV-s
pV-s
V/s
ps
ps
%
Deg
dBc
dBc
R
L
= 50DAC Operating in Latched Mode
(Note 3)
R
L
= 50DAC Operating in Latched Mode
(Note 3)
R
L
= 50DAC Operating in Latched Mode
(Note 3)
R
L
= 50 (Note 3)
R
L
= 50 (Note 3)
f
CLK
= 40MHz, f
OUT
= 2.02MHz, 20MHz Span
f
CLK
= 80MHz, f
OUT
= 2.02MHz, 40MHz Span
-
-
-
-
-
-
-
FN4133 Rev 4.00
May 2003
Page 3 of 11
HI5735
Electrical Specifications
PARAMETER
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, V
REF
Internal Reference Voltage Drift
Internal Reference Output Current Sink/Source
Capability
Internal Reference Load Regulation
Input Impedance at REF OUT pin
Amplifier Large Signal Bandwidth (0.6V
P-P
)
Amplifier Small Signal Bandwidth (0.1V
P-P
)
Reference Input Impedance
Reference Input Multiplying Bandwidth (CTL IN)
DIGITAL INPUTS
(D9-D0, CLK, INVERT)
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Input Logic Current, I
IH
Input Logic Current, I
IL
Digital Input Capacitance, C
IN
TIMING CHARACTERISTICS
Data Setup Time, t
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLK Pulse Width, t
PW1
, t
PW2
POWER SUPPLY CHARACTERISITICS
I
EEA
I
EED
I
CCD
Power Dissipation
Power Supply Rejection Ratio
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(typically 1.28mA). Ideally the
ratio should be 16.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25
o
C. 100% production tested at temperature extremes for military temperature devices, sample tested for
industrial temperature devices.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
(Note 4)
(Note 4)
(Note 4)
(Note 4)
V
CC
5%,
V
EE
5%
-
-
-
-
-
42
70
13
650
5
50
85
20
-
-
mA
mA
mA
mW
A/V
See Figure 1 (Note 3)
See Figure 1 (Note 3)
See Figure 1 (Note 3)
See Figure 1 (Note 3)
3.0
0.5
-
3.0
2.0
0.25
4.5
-
-
-
-
-
ns
ns
ns
ns
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 3)
2.0
-
-
-
-
-
-
-
-
3.0
-
0.8
400
700
-
V
V
A
A
pF
(Note 4)
(Note 3)
(Note 3)
I
REF
= 0 to I
REF
= -125A
(Note 3)
Sine Wave Input, to Slew Rate Limited (Note 3)
Sine Wave Input, to -3dB Loss (Note 3)
(Note 3)
R
L
= 50, 100mV Sine Wave, to -3dB Loss at I
OUT
(Note 3)
-1.27
-
-125
-
-
-
-
-
-
-1.23
50
-
50
1.4
3
10
12
200
-1.17
-
+50
-
-
-
-
-
-
V
V/
o
C
A
V
k
MHz
MHz
k
MHz
AV
EE
, DV
EE
= -4.94 to -5.46V, V
CC
= +4.75 to +5.25V, V
REF
= Internal T
A
= 25
o
C for All Typical Values
TEST CONDITIONS
MIN
TYP
MAX
UNITS
FN4133 Rev 4.00
May 2003
Page 4 of 11
HI5735
Timing Diagrams
CLK
50%
V
D11-D0
GLITCH AREA =
1
/
2
(H x W)
HEIGHT (H)
1
/
2
LSB ERROR BAND
I
OUT
WIDTH (W)
t(ps)
t
PD
t
SETT
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
t
PW1
t
PW2
CLK
t
SU
t
HLD
D11-D0
t
SU
t
HLD
t
SU
t
HLD
50%
t
PD
I
OUT
t
PD
t
PD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
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