®
HIP1013
Data Sheet
August 2004
FN4516.3
Low Cost Dual Power Distribution
Controller
The HIP1013 is a low cost HOT SWAP dual supply power
distribution controller. Two external N-Channel MOSFETs are
driven to distribute power while providing load fault isolation. At
turn-on, the gate of each external N-Channel MOSFET is
charged with a 10µA current source. Capacitors on each gate
(see the Typical Application Diagram), create a programmable
ramp (soft turn-on) to control inrush currents. A built in charge
pump supplies the gate drive for the 12V supply N-Channel
MOSFET switch.
Over current protection is facilitated by two external current
sense resistors. When the current through either resistor
exceeds the user programmed value the N-Channel MOSFETs
are latched off by the HIP1013. The controller is reset by a
rising edge on either PWRON pin.
Choosing the voltage selection mode the HIP1013 controls
either +12V/5V or +3.3V/+5V supplies.
Although pin compatible with the HIP1012 device, the HIP1013
does not offer current regulation during an OC event.
Features
• HOT SWAP Dual Power Distribution Control for +5V and
+12V or +5V and +3.3V
• Provides Fault Isolation
• Charge Pump Allows the Use of N-Channel MOSFETs
• Redundant Power On Controls
• Power Good and Over Current Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Pb-free Available
Applications
• Power Distribution Control
• Hot Plug™ Components
Typical Application Diagram
C
PUMP
R
SENSE
R
LOAD
HIP1013
12V
3/12VISEN
R
ILIM
GND
C
PUMP
5V
Ordering Information
PART
NUMBER
HIP1013CB
HIP1013CBZA (Note)
TEMP.
RANGE (°C)
-0 to 70
-0 to 70
PACKAGE
14 Ld SOIC
14 Ld SOIC
(Pb-free)
PKG.
DWG. #
M14.15
M14.15
V
DD
3/12VS
C
GATE
3/12VG
V
DD
POWER ON
INPUTS
R
ILIM
M/PON1
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
*Tape & Reel packaging available with “-T” suffix..
NC
PWRON2
PGOOD
5VG
5VS
5ISEN
5V
C
GATE
R
SENSE
R
LOAD
Pinout
HIP1013 (SOIC)
TOP VIEW
3/12VS
3/12VG
1
2
14 3/12VISEN
13 R
ILIM
12 GND
11 C
PUMP
10 NC
9 PGOOD
8 5VISEN
V
DD
3
MODE/ 4
PWRON1
PWRON2 5
5VG 6
5VS 7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 1999, 2004. All Rights Reserved
Hot Plug™ is a trademark of Core International, Inc.
All other trademarks mentioned are the property of their respective owners.
R
SENSE
TO LOAD
12VIN
Functional Diagram
12VS
12V
100µA
OC
12VG
10µA
18V
18V
POR
GND
ENABLE
QPUMP
V
DD
+
R
ILIM
12ISEN
2
-
R
ILIM
R QN
R
Q
S
RISING
EDGE
RESET
C
GATE
V
DD
MODE/
PWRON1
HIP1013
C
PUMP
TO V
DD
C
PUMP
PWRON2
12V
12V
10µA
5VG
+
PGOOD
NC
C
GATE
PGOOD
-
OC
5VS
HIP1013
5ISEN
R
SENSE
TO LOAD
5VIN
HIP1013
Pin Description
PIN NO.
1
SYMBOL
12VS
FUNCTION
12V Source
DESCRIPTION
Connect to source of associated external N-Channel MOSFET switch to sense output
voltage.
Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this
node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to
≈
17.4V
by a 10µA current source when in 5V/12V mode of operation, otherwise capacitor will be
charged to
≈
11.4V.
Connect to 12V supply. This can be either connected directly to the +12V rail supplying
the load voltage or to a dedicated V
DD
+12V supply.
PWRON1 and PWRON2 are used to turn-on and reset the chip. Both outputs turn-on
when either pin is driven low. After an over current limit fault, the chip is reset by the rising
edge of a reset signal applied to either PWRON pin. Each input has 100µA pull up
capability which is compatible with 3V and 5V open drain and standard logic. PWRON1
is also used to invoke 3.3V control operation in preference to +12V control. By tying pin
4 to pin 3 the charge pump is disabled and the UV threshold also shifts to
≈
2.8V.
Connect to the gate of the external 5V N-Channel MOSFET. A capacitor from this node
to ground sets the turn-on ramp. At turn-on this capacitor will be charged to
≈
11.4V by a
10µA current source.
Connect to the source side of 5V external N-Channel MOSFET switch to sense output
voltage.
Connect to the load side of the 5V sense resistor to measure the voltage drop across this
resistor between 5VS and 5VISEN pins.
PGOOD is driven by an open drain N-Channel MOSFET. It is pulled low when either
output voltage is not within specification or and OC condition exists.
No Connection.
C
PUMP
GND
R
ILIM
Charge Pump Capacitor
Chip Ground
Current Limit Set Resistor
A resistor connected between this pin and ground determines the current level at which
current limit is activated. This current is determined by the ratio of the R
ILIM
resistor to
the sense resistor (R
SENSE
). The current at current limit onset is equal to
10µA x (R
ILIM
/ R
SENSE
).
Connect to the load side of sense resistor to measure the voltage drop across this
resistor.
Connect a 0.1µF capacitor between this pin and V
DD
(Pin 3).
2
12VG
12V Gate
3
V
DD
Chip Supply
4
MODE/
PWRON1
Power ON/ Reset invokes
3.3V operation when
shorted to V
DD
, Pin 3.
Power ON/Reset
5
PWRON2
6
5VG
5V Gate
7
5VS
5V Source
8
5VISEN
5V Current Sense
9
PGOOD
Power Good Indicator
10
11
12
13
14
12VISEN
12V Current Sense
3
HIP1013
Absolute Maximum Ratings
T
A
= 25°C
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V
3/12VG, C
PUMP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 25V
3/12VISEN, 3/12VS . . . . . . . . . . . . . . . . . . . . . . . -5V to V
DD
+ 0.3V
5VISEN, 5VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 7.5V
PGOOD, R
ILIM
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V
MODE/PWRON1, PWRON2, 5VG . . . . . . . . . . -0.3V to V
DD
+ 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2)
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
V
DD
Supply Voltage Range . . . . . . . . . . . . . . . . . . . +10.5V to +16V
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER
CONTROL SECTION
Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
V
DD
= 12V, C
VG
= 0.01µF, R
SENSE
= 0.1Ω, C
BULK
= 220µF, ESR = 0.5Ω, T
A
= T
J
= 0°C to 70°C, Unless
Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
IL
OC
Lrt
RT
SHORT
t
ON12V
t
ON5V
I
ON
12V
VUV
5V
VUV
3.3V
VUV
V12VG
3/5VG
R
ILIM
= 10kΩ
Current Overload, R
ILIM
= 10kΩ, R
SHORT
= 6.0Ω
C
VG
= 0.01µF
C
VG
= 0.01µF
C
VG
= 0.01µF
C
VG
= 0.01µF
85
-
-
-
-
8
10.5
4.35
2.65
100
2
500
12
5
10
10.8
4.5
2.8
17.3
11.9
115
-
1000
-
-
12
11.0
4.65
2.95
17.9
-
mV
µs
ns
ms
ms
µA
V
V
V
V
V
Over Current Limit Response Time
Response Time To Dead Short
12V Gate Turn-On Time
5V Gate Turn-On Time
Gate Turn-On Current
12V Under Voltage Threshold
5V Under Voltage Threshold
3.3V Under Voltage Threshold
Charge pumped 12VG Voltage
3/5VG High Voltage
C
PUMP
= 0.1µF
16.8
11.2
SUPPLY CURRENT AND IO SPECIFICATIONS
V
DD
Supply Current
V
DD
POR Rising Threshold
V
DD
POR Falling Threshold
PWRON Pull-up Voltage
PWRON Rising Threshold
PWRON Hysteresis
PWRON Pull-Up Current
R
ILIM
Pin Current Source Output
Charge Pump Output Current
Charge Pump Output Voltage
Charge Pump Output Voltage - Loaded
Charge Pump POR Rising Threshold
Charge Pump POR Falling Threshold
I
VDD
POR
rvth
POR
fvth
PWRN_V
PWR_Vth
PWR_hys
PWRN_I
R
ILIM
_Io
Qpmp_Io
Qpmp_Vo
Qpmp_VIo
Qpmp+Vth
Qpmp-Vth
C
PUMP
= 0.1µF, C
PUMP
= 16V
No load
Load current = 100µA
PWRON pins open
4
9.5
9.3
1.8
1.1
0.1
60
90
400
17.2
16.2
15.6
15.2
8
10.0
9.8
2.4
1.5
0.2
80
100
590
17.4
16.7
16
15.7
10
10.5
10.3
3.2
2
0.3
100
110
800
-
-
16.5
16.2
mA
V
V
V
V
V
µA
µA
µA
V
V
V
V
4
HIP1013
Typical Performance Curves
8.4
8.2
SUPPLY CURRENT(mA)
105
8.0
7.8
7.6
7.4
7.2
-40
CURRENT (µA)
104
103
-30
-20 -10
0
10
20
30
40
50
60
70
80
102
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 1. SUPPLY CURRENT
FIGURE 2. R
ILIM
SOURCE CURRENT
11.00
4.615
2.888
12V UV THRESHOLD (V)
4.610
5V UV
2.886
10.98
4.605
3.3V UV
4.600
2.884
10.96
2.882
10.94
-40
-20
0
20
40
60
80
4.595
-40
-20
0
20
40
60
80
2.880
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. 12V UV THRESHOLD
FIGURE 4. 3.3V/5V UV THRESHOLD
17.36
11.935
11.930
3.3V, 5V GATE DRIVE (V)
17.6
17.34
12V GATE DRIVE (V)
12V VG
17.32
11.925
11.920
11.915
5V VG
17.28
11.905
17.26
-40
11.900
80
11.910
17.4
CHARGE PUMP VOLTAGE
NO LOAD
VOLTAGE (V)
17.2
17.30
17.0
CHARGE PUMP VOLTAGE
100µA LOAD
16.8
-20
0
20
40
60
16.6
-40
-20
TEMPERATURE (°C)
0
20
40
TEMPERATURE (°C)
60
80
FIGURE 5. 12V, 5V GATE DRIVE
FIGURE 6. CHARGE PUMP VOLTAGE
5
3.3V UV THRESHOLD (V)
5V UV THRESHOLD (V)
Embedded System
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