74LCXZ16245_05 datasheet, PDF - EEWORLD Datasheet

74LCXZ16245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs and Outputs

March 2002

Revised June 2005

74LCXZ16245

Low Voltage 16-Bit Bidirectional Transceiver

with 5V Tolerant Inputs and Outputs

General Description

The LCXZ16245 contains sixteen non-inverting bidirec-

tional buffers with 3-STATE outputs and is intended for bus

oriented applications. The device is designed for low volt-

age (2.7V or 3.3V) V

CC

applications with capability of inter-

facing to a 5V signal environment. The device is byte

controlled. Each byte has separate control inputs which

could be shorted together for full 16-bit operation. The T/R

inputs determine the direction of data flow through the

device. The OE inputs disable both the A and B ports by

placing them in a high impedance state.

When V

CC

is between 0V and 1.5V, the LCXZ16245 is on

the high impedance state during power-up or power-down.

This places the outputs in the high impedance (Z) state

preventing intermittent low impedance loading or glitching

in bus oriented applications.

The LCXZ16245 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Features

s

5V tolerant inputs and outputs

s

2.7V–3.6V V

CC

specifications provided

s

4.5 ns t

PD

max (V

CC

3.3V), 20

P

A I

CC

max

s

Power-down high impedance inputs and outputs

s

Supports live insertion/withdrawal (Note 1)

s

r

24 mA output drive (V

CC

3.0V)

s

Implements patented noise/EMI reduction circuitry

s

Latch-up performance conforms to the requirements of

JESD78

s

ESD performance:

Human body model

!

2000V

Machine model

!

200V

Note 1:

To ensure the high-impedance state during power up or down, OE

should be tied to V

CC

through a pull-up resistor: the minimum value or the

resistor is determined by the current-sourcing capability of the driver.

Ordering Code:

Order Number

74LCXZ16245MTD

Package Number

MTD48

Package Description

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

DS500580

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74LCXZ16245

Connection Diagram

Pin Assignment for SSOP and TSSOP

Pin Descriptions

Pin Names

OE

n

T/R

n

A

0

–A

15

B

0

–B

15

NC

Description

Output Enable Input

Transmit/Receive Input

Side A Inputs or 3-STATE Outputs

Side B Inputs or 3-STATE Outputs

No Connect

Truth Tables

Inputs

OE

1

L

H

Inputs

OE

2

L

H

T/R

2

L

H

X

Outputs

Bus B

8

–B

15

Data to Bus A

8

–A

15

Bus A

8

–A

15

Data to Bus B

8

–B

15

HIGH Z State on A

8

–A

15

, B

8

–B

15

T/R

1

L

H

X

Outputs

Bus B

0

–B

7

Data to Bus A

0

–A

7

Bus A

0

–A

7

Data to Bus B

0

–B

7

HIGH Z State on A

0

–A

7

, B

0

–B

7

H HIGH Voltage Level

L LOW Voltage Level

X Immaterial

Z High Impedance

Logic Diagram

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2

74LCXZ16245

Absolute Maximum Ratings

(Note 2)

Symbol

V

CC

V

I

V

O

I

IK

I

OK

I

O

I

CC

I

GND

T

STG

Parameter

Supply Voltage

DC Input Voltage

DC Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Source/Sink Current

DC Supply Current per Supply Pin

DC Ground Current per Ground Pin

Storage Temperature

Value

Conditions

Units

V

Output in 3-STATE

Output in HIGH or LOW State (Note 3)

V

I

GND

V

O

GND

V

O

!

V

CC

V

mA

0.5 to

7.0

0.5 to

7.0

0.5 to

7.0

0.5 to V

CC

0.5

50

r

50

r

100

r

100

65 to

150

q

C

Recommended Operating Conditions

(Note 4)

Symbol

V

CC

V

I

V

O

I

OH

/I

OL

T

A

Supply Voltage

Input Voltage

Output Voltage

Output Current

Free-Air Operating Temperature

Input Edge Rate, V

IN

0.8V–2.0V, V

CC

3.0V

HIGH or LOW State

3-STATE

V

CC

V

CC

3.0V

3.6V

2.7V

3.0V

Parameter

Operating

Min

2.7

0

Max

3.6

5.5

V

CC

5.5

Units

V

mA

r

24

r

12

40

0

85

10

q

C

ns/V

'

t/

'

V

Note 2:

The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-

mended Operating Conditions” table will define the conditions for actual device operation.

Note 3:

I

O

Absolute Maximum Rating must be observed.

Note 4:

Unused inputs or I/O's must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Symbol

V

IH

V

IL

V

OH

Parameter

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Voltage

I

OH

I

OH

I

OH

I

OH

V

OL

LOW Level Output Voltage

I

OL

I

OL

I

OL

I

OL

I

OZ

I

OFF

I

PU/PD

I

CC

Input Leakage Current

3-STATE I/O Leakage

Power-Off Leakage Current

Power-Up/Power-Down

3-STATE Output Current

Quiescent Supply Current

Increase in I

CC

per Input

Conditions

V

CC

(V)

2.7

3.6

2.7

3.6

T

A

40

q

C to

85

q

C

Max

Units

V

Min

2.0

0.8

V

CC

0.2

2.2

2.4

2.2

0.2

0.4

0.55

V

100

P

A

12 mA

18 mA

24 mA

100

P

A

12 mA

16 mA

24 mA

2.7

3.6

2.7

3.0

2.7

3.6

2.7

3.0

2.7

3.6

2.7

3.6

0

0 - 1.5

2.7–3.6

V

0

d

V

I

d

5.5V

0

d

V

O

d

5.5V

V

I

V

O

V

I

V

I

V

IH

V

IH

or V

IL

5.5V

V

I

or V

O

r

5.0

r

5.0

10

P

A

P

A

P

A

P

A

P

A

P

A

0.5V to V

CC

V

CC

or GND

V

CC

or GND

V

CC

0.6V

r

5.0

225

3.6V

d

V

I

, V

O

d

5.5V (Note 5)

r

225

500

'

I

CC

Note 5:

Outputs disabled or 3-STATE only.

3

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74LCXZ16245

AC Electrical Characteristics

T

A

Symbol

Parameter

V

CC

C

L

Min

t

PHL

t

PLH

t

PZL

t

PZH

t

PLZ

t

PHZ

t

OSHL

t

OSLH

Output to Output Skew (Note 6)

Output Disable Time

Propagation Delay

A

n

to B

n

or B

n

to A

n

Output Enable Time

1.0

40

q

C to

85

q

C, R

L

500

:

V

CC

C

L

2.7V

50 pF

Max

5.2

7.2

6.9

ns

Units

3.3V

r

0.3V

50 pF

Max

4.5

6.5

6.4

1.0

Min

1.0

Note 6:

Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The

specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guaranteed by design.

Dynamic Switching Characteristics

Symbol

V

OLP

V

OLV

Parameter

Quiet Output Dynamic Peak V

OL

Quiet Output Dynamic Valley V

OL

C

L

C

L

50 pF, V

IH

50 pF, V

IH

Conditions

3.3V, V

IL

3.3V, V

IL

0V

V

CC

(V)

3.3

T

A

25

q

C

0.8

Units

V

Typical

0.8

Capacitance

Symbol

C

IN

C

I/O

C

PD

Input Capacitance

Input/Output Capacitance

Power Dissipation Capacitance

Parameter

V

CC

V

CC

V

CC

Open, V

I

3.3V, V

I

3.3V, V

I

Conditions

0V or V

CC

0V or V

CC

0V or V

CC

, f

10 MHz

Typical

7

8

20

Units

pF

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4

74LCXZ16245

AC LOADING and WAVEFORMS

Generic for LCX Family

FIGURE 1. AC Test Circuit (C

L

includes probe and jig capacitance)

Test

t

PLH

, t

PHL

t

PZL

, t

PLZ

t

PZH

, t

PHZ

6V at V

CC

Switch

Open

3.3

r

0.3V, and 2.7V

GND

Waveform for Inverting and Non-Inverting Functions

3-STATE Output High Enable and

Disable Times for Logic

Propagation Delay. Pulse Width and t

rec

Waveforms

Setup Time, Hold Time and Recovery Time for Logic

3-STATE Output Low Enable and

Disable Times for Logic

FIGURE 2. Waveforms

(Input Characteristics; f =1MHz, t

r

= t

f

= 3ns)

Symbol

V

mi

V

mo

V

x

V

y

V

CC

3.3V

r

0.3V

1.5V

V

OL

0.3V

V

OH

0.3V

t

rise

and t

fall

2.7V

1.5V

V

OL

0.3V

V

OH

0.3V

5

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