DM74ALS646 Octal 3-STATE Bus Transceiver and Register
October 1986
Revised June 2001
DM74ALS646
Octal 3-STATE Bus Transceiver and Register
General Description
This device incorporates an octal bus transceiver and an
octal D-type register configured to enable multiplexed
transmission of data from bus to bus or internal register to
bus.
This bus transceiver features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic level drive provides this device with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without the need for
interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The registers in the DM74ALS646 are edge-triggered D-
type flip-flops. On the positive transition of the clock (CAB
or CBA), the input bus data is stored into the appropriate
register. The CAB input controls the transfer of data into
the A register and the CBA input controls the B register.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data, and a HIGH level selects
stored data. The select controls have a “make before
break” configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between store and real-time data.
The enable G and direction control pins provide four modes
of operation: real-time data transfer from bus A to B, real-
time data transfer from bus B to A, real-time bus A and/or B
data transfer to internal storage, or internally stored data
transfer to bus A or B.
When the enable G pin is LOW, the direction pin selects
which bus receives data. When the enable G pin is HIGH,
both buses become disabled yet their input function is still
enabled.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
3-STATE buffer outputs drive bus lines directly
s
Multiplexed real-time and stored data
s
Independent registers for A and B buses
Ordering Code
Order Number
DM74ALS646WM
DM74ALS646NT
Package Number
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS009172
www.fairchildsemi.com
DM74ALS646
Connection Diagram
Function Table
Inputs
G
X
X
H
H
L
L
L
L
DIR CAB CBA SAB SBA
X
X
X
X
L
L
H
H
Data I/O (Note 1)
Operation or Function
A1 thru A8
Input
Not Specified
Input
Input
Output
Output
Input
Input
B1 thru B8
Not Specified Store A, B Unspecified
Input
Input
Input
Input
Input
Output
Output
Store B, A Unspecified
Store A and B Data
Isolation, Hold Storage
Real-Time B Data to a Bus
Stored B Data to a Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
↑
X
X
X
X
X
X
X
X
L
H
X
X
X
X
L
H
X
X
↑
↑
H/L
X
H/L
X
X
↑
H/L
X
X
X
H/L
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don’t Care (Either LOW or HIGH Logic Levels including transitions)
H/L
=
Either LOW or HIGH Logic Level excluding transitions
↑ =
Positive going edge of pulse
Note 1:
The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
www.fairchildsemi.com
2
DM74ALS646
Absolute Maximum Ratings
(Note 2)
Supply Voltage
Input Voltage
Control Inputs
I/O Ports
Operating Free-Air Temperature Range
Storage Temperature Range
Typical
θ
JA
N Package
M Package
44.5
°
C/W
80.5
°
C/W
7V
5.5V
0
°
C to
+
70
°
C
Note 2:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
7V
−
65
°
C to
+
150
°
C
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
f
CLK
t
W
t
SU
t
H
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
Pulse Duration, Clocks LOW or HIGH
Data Setup Time, A before CAB or B before CBA (Note 3)
Data Hold Time, A after CAB or B after CBA (Note 3)
Free Air Operating Temperature
10
↑
0
↑
70
0.8
Parameter
Min
Nom
5
Max
5.5
Units
V
V
V
mA
mA
MHz
ns
ns
ns
−
15
24
40
°
C
Note 3:
↑ =
With reference to the LOW-to-HIGH transition of the respective clock.
Electrical Characteristics
over recommended free air temperature range
Symbol
Parameter
V
IC
V
OH
Input Clamp Voltage
HIGH Level
Output Voltage
V
OL
LOW Level
Output Voltage
I
I
I
IH
I
IL
I
O
I
CC
Input Current at Maximum
Input Voltage
HIGH Level Input Current
LOW Level
Input Current
Output Drive Current
Supply Current
V
CC
=
Max,
V
I
=
0.4V, (Note 4)
V
CC
=
Max, V
O
=
2.25V
V
CC
=
Max
Outputs HIGH
Outputs LOW
Outputs Disabled
Note 4:
For I/O ports the 3-STATE output currents (I
OZH
and I
OZL
) are included in the I
IH
and I
IL
parameters.
Test Conditions
I
OH
= −0.4
mA
I
OH
= −3
mA
I
OH
=
Max
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
48 mA
Min
V
CC
−
2
2.4
2
Typ
Max
−1.2
Units
V
V
V
CC
=
Min, I
I
= −18
mA
V
CC
=
4.5V to 5.5V
V
CC
=
Min
V
CC
=
Min
3.2
0.25
0.35
0.35
0.4
0.5
0.5
100
100
20
−200
−200
µA
µA
µA
mA
mA
V
V
CC
=
Max
I/O Ports, V
I
=
5.5V
Control Inputs, V
I
=
7V
V
CC
=
Max, V
I
=
2.7V (Note 4)
Control Inputs
I/O Ports
−30
47
55
55
−112
76
88
88
3
www.fairchildsemi.com
京公网安备 11010802033920号
EEWORLD
