CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
DC CHARACTERISTICS
V
DD
Supply Range - Operating
V
DD
Supply Range - EEPROM
Programming
V
DD
Supply Current
AVDD Supply Range
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, R
SET
= 24.9kΩ; Unless Otherwise Specified.
Typicals are at T
A
= 25°C
SYMBOL
TEST CONDITIONS
TEMP (°C)
MIN
TYP
MAX
UNITS
V
DD
V
DD
I
DD
AVDD
(Note 4)
VDD range 2.6V - 3.6V
VDD range 2.25V - 3.6V
Full
Full
Full
Full
2.25
2.25
-
4.5
4.5
-
-
-
-
-
-
7
-
-
-
20
-
-
1:20
8
-
<10
-
-
0.22 * VDD
25
-
-
3.6
3.6
50
18
13
25
7
±1
±2
±8
-
200
45
-
-
13
-
-
0.3*VDD
-
35
-
0.4
V
V
μA
V
V
μA
Bits
LSB
LSB
LSB
μA
kΩ
kΩ
V/V
μs
V
mV
V
V
V
μA
V
V
AVDD Supply Current
SET Voltage Resolution
SET Differential Nonlinearity
SET Zero-Scale Error
SET Full-Scale Error
SET Current
SET External Resistance
IAVDD
SET
VR
SET
DN
SET
ZSE
SET
FSE
ISET
SET
ER
(Note 2)
Full
Full
-
7
-
-
-
-
10
2.25
-
-
VSET + 0.5V
-
0.7*VDD
-
-
15
0.4
-
Monotonic over temperature
Full
Full
Full
Through R
SET
(Note 5)
To GND, AVDD = 20V
To GND, AVDD = 4.5V
Full
Full
Full
Full
Full
Full
AVDD to SET Voltage Attenuation
OUT Settling Time
OUT Voltage Range
SET Voltage Drift
SDA, SCL, WP Input Logic High
SDA, SCL, WP Input Logic High
SDA, SCL, WP Hysteresis
WP IL
SDA, SCL Output Logic High
SDA, SCL Output Logic Low
AVDD to
SET
OUT
ST
V
OUT
SET
VD
VIH
VIL
(Note 3)
to
±0.5
LSB Error Band (Note 3)
(Note 3)
25 to 55
Full
Full
(Note 3)
IL
WPN
VOH
S
VOL
S
@ 3mA
@ 3mA
Full
Full
Full
Full
3
FN6189.1
April 4, 2006
ISL45041
Electrical Specifications
PARAMETER
I
2
C
SCL Clock Frequency
I
2
C Clock High Time
I
2
C Clock Low Time
I
2
C Spike Rejection Filter Pulse Width
I
2
C Data Set-up Time
I
2
C Data Hold Time
I
2
C SDA, SCL Input Rise Time
I
2
C SDA, SCL Input Fall Time
I
2
C Bus Free Time Between Stop and
Start
I
2
C Repeated Start Condition Set-up
I
2
C Repeated Start Condition Hold
I
2
C Stop Condition Set-up
I
2
C Bus Capacitive Load
F
SCL
t
SCH
t
SCL
t
DSP
t
SDS
t
SDH
t
ICR
t
ICF
t
BUF
t
STS
t
STH
t
SPS
Cb
Dependent on Load (Note 6)
(Note 6)
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
0
0.6
1.3
0
100
0
-
-
1.3
0.6
0.6
0.6
-
-
-
-
-
-
-
20 + 0.1*
Cb
20 + 0.1*
Cb
-
-
-
-
-
400
-
-
50
-
900
1000
300
-
-
-
-
400
kHz
μs
μs
ns
ns
ns
ns
ns
μs
μs
μs
μs
pF
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, R
SET
= 24.9kΩ; Unless Otherwise Specified.
Typicals are at T
A
= 25°C
(Continued)
SYMBOL
TEST CONDITIONS
TEMP (°C)
MIN
TYP
MAX
UNITS
Capacitance on SDA
Capacitance on SCL
C
SDA
C
S
WP = 0
WP = 1
Full
Full
-
-
-
-
-
-
-
10
10
22
100
pF
pF
Write Cycle Time
NOTES:
2. Tested at AVDD = 20V.
T
W
Full
-
ms
3. Simulated and Determined via Design and NOT Directly Tested.
4. Simulated Maximum Current Draw when Programming EEPROM is 23mA, should be considered when designing Power Supply.
5. A Typical Current of 20μA is Calculated using the AVDD = 10V and RSET = 24.9kΩ. The maximum suggested SET Current should be 120μA.
6. Simulated and Designed According to I
2
C Specifications.
4
FN6189.1
April 4, 2006
ISL45041
Application Information
This device provides the ability to reduce the flicker of an
LCD panel by adjustment of the VCOM voltage during
production test and alignment. A 128-step resolution is
provided under digital control, which adjusts the sink current
of the output. The output is connected to an external voltage
divider, so that the device will have the capability to reduce
the voltage on the output by increasing the output sink
current.
AVDD
ISL45041
OUT
R
SET
I
SET
R
2
TABLE 1.
SETTING VALUE
1
10
20
30
40
50
VOUT
5.468
5.313
5.141
4.969
4.797
4.625
4.453
4.281
4.109
3.936
3.764
3.592
3.282
AVDD
R
1
-
+
60
70
80
90
100
110
SET
FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE
128
The adjustment of the output is provided by the 2 wire I
2
C
serial interface.
R
SET
Resistor
The external R
SET
resistor sets the full-scale sink current
that determines the lowest voltage of the external voltage
divider R
1
and R
2
(Figure 1). The maximum I
SET
current has
to be less than 120μA. The minimum RSET resistor with
AVDD equal to 10V is 4.17kΩ (10V/(20*120μA). Typical
applications with AVDD equal to 10V set R
SET
equal to
24.9kΩ for a set current equal to 20μA.
Expected Output Voltage
The ISL45041 provides an output sink current which lowers
the voltage on the external voltage divider (VCOM output
voltage). Equation 1 and Equation 2 can be used to calculate
the output current (IOUT) and output voltage (VOUT) values.
Setting
AVDD
-
-
IOUT
= --------------------
X
----------------------------
128
20
(
RSET
)
R2
Setting
R1
-
-
-
VOUT
=
⎛
---------------------
⎞
AVDD
⎛
1
– --------------------
X
----------------------------
⎞
⎝
R1
+
R2
⎠
⎝
128
20
(
RSET
)⎠
NOTE: Where setting is an integer between 1 and 128.
(EQ. 1)
Ramp-Up of the VDD Power Supply
It is required that the ramp-up from 10% VDD to 90% VDD
level be achieved in less than or equal to 10 ms to assure
that the EEPROM and Power-on-reset circuits are
synchronized and the correct value is read from the
EEPROM Memory.
(EQ. 2)
Table 1 gives the calculated value of VOUT for the eval
board using the on board resistors values of: RSET = 24.9k,
R1 = 200k, R2 = 243k, and AVDD = 10V.
I
2
C Timing Diagram
Figure 2 shows the I
2
C timing diagram and expected scope
photos of SCL and SDA when writing all zeros or all ones.
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