ISL45042AIRZ-TK datasheet, PDF

DATASHEET

ISL45042A

LCD Module Calibrator

The V

COM

voltage of an LCD panel needs to be adjusted to

remove flicker. The ISL45042A can be used to digitally

adjust a panel’s V

COM

voltage by controlling its output sink

current. The output of the ISL45042A is connected to an

external voltage divider and an external V

COM

buffer

amplifier. In this application, the user can control the V

COM

voltage with 7-bit accuracy (128 steps). Once the desired

V

COM

setting is obtained, the settings can be stored in the

non-volatile EEPROM memory, which would then be

automatically recalled during every power-up.

The V

COM

adjustment and non-volatile memory

programming is through a single interface pin (CTL). Once

the desired programmed value is obtained, the Counter

Enable pin (CE) can be used to prevent further adjustment

or programming.

The full-scale sink current of the ISL45042A is set using an

external resistor connected to the SET pin. The full-scale

sink current determines the lowest voltage of the external

voltage divider.

The ISL45042A is available in an 8 Ld 3mmx3mm TDFN

package with a maximum thickness of 0.8mm for ultra thin

LCD panel design.

FN6158

Rev 4.00

Jul 9, 2008

Features

• 128-Step Adjustable Sink Current Output

• 2.6V to 3.6V Logic Supply Voltage Operating Range

• 4.5V to 20V Analog Supply Voltage Range

• Rewritable EEPROM for storing the optimum V

COM

value

• Output Adjustment Enable/Disable Control

• Output Guaranteed Monotonic Over-Temperature

• Two Pin Adjustment, Programming and Enable

• Ultra Thin 8 Ld 3mmx3mm DFN (0.8mm max)

• Pb-Free (RoHS compliant)

Applications

• LCD Panels

Ordering Information

PART NUMBER

(Note)

ISL45042AIRZ

ISL45042AIRZ-T*

TEMP.

RANGE

PART

(°C)

MARKING

42AZ

PACKAGE

(Pb-Free)

PKG.

DWG. #

L8.3x3A

-40 to +85 8 Ld 3x3 TDFN

Tape and Reel

-40 to +85 8 Ld 3x3 TDFN

Tape and Reel

Pinout

ISL45042A

(8 LD TDFN)

TOP VIEW

OUT 1

AVDD 2

N/C 3

GND 4

8

7

6

5

SET

CE

CTL

V

DD

ISL45042AIRZ-TK* 42AZ

L8.3x3A

*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special

Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS

compliant and compatible with both SnPb and Pb-free soldering

operations). Intersil Pb-free products are MSL classified at Pb-free peak

reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

FN6158 Rev 4.00

Jul 9, 2008

Page 1 of 8

ISL45042A

Pin Descriptions

OUT

FUNCTION

Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink

current divided by 128. See SET pin function in “Pin Descriptions” on page 2 for the maxim adjustable sink current setting.

High-Voltage Analog Supply. Connects to top of external resistor divider to determine the V

COM

voltage. Typically 10V to 20V. Bypass

to GND with 0.1µF de-coupling capacitor.

No Connect. Not internally connected.

Ground connection.

ISL45042A power supply input. Bypass to GND with 0.1µF de-coupling capacitor.

Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments

the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high

transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage

at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter.

See EEPROM Programming section in “Electrical Specifications” table on page 4 for details.

Counter Enable Pin. Connect CE to VDD to enable adjustment of the output sink current. Float or connect CE to GND to prevent

further adjustment or programming (note: the CE pin has an internal pull-down resistor).

Maximum Sink Current Adjustment Point. Connect a resistor from the SET pin to GND to set the maximum adjustable sink current of

the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.

AVDD

N/C

GND

V

DD

CTL

CE

SET

Block Diagram

ISL45042A

CE

400k

TO

500k

UP

DWN

CTL

DIGITAL INTERFACE

WITH THRESHOLD

SENSORS

PWRUP

POR

PRGM

UP/DOWN COUNTER

WITH PRESET

LATCHES

ANALOG DCP AND

CURRENT OUTPUT

BLOCK

SET

AVDD

IBIAS

IOUT

READ

PRGM MEMORY

POR

EEPROM

OR

PRGM

NVL MEMORY

GND

VDD

FN6158 Rev 4.00

Jul 9, 2008

Page 2 of 8

ISL45042A

Absolute Maximum Ratings

V

DD

to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4V

Input Voltages to GND

SET, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V

AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V

CTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +17V

Output Voltages to GND

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V

ESD Rating

Human Body Model

Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75kV

CTL to GND (No EEPROM Disruption) . . . . . . . . . . . . . . . .8kV

Thermal Information

Thermal Resistance (Typical, Notes 1, 2)



JA

(°C/W)



JC

(°C/W)

8 Ld TDFN Package. . . . . . . . . . . . . . .

47

12

Moisture Sensitivity (see Technical Brief TB363)

All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1

Maximum Junction Temperature (Plastic Package) . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Erase/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 years @ +85°C

Operating Conditions

Temperature Range

ISL45042AIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

1.



JA

is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. For



JC

, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications

Test Conditions: V

DD

= 3V, AV

DD

= 10V, OUT = 5V, R

SET

= 24.9k; Unless Otherwise Specified.

Typicals are at T

A

= +25°C

SYMBOL

TEST CONDITIONS

TEMP

(°C)

MIN

(Note 9)

TYP

MAX

(Note 9) UNITS

PARAMETER

DC CHARACTERISTICS

V

DD

Supply Range

V

DD

For Programming

For Operation

0 to 85

Full

3

2.6

-

4.5

-

0.7*V

DD

0.2*V

DD

20

-

0.64*V

DD

-

4.9

-

10

-

1

-

3.6

50

20

0.8*V

DD

0.3*V

DD

-

200

10

-

0.4

-

15.75

V

µA

V

µA

V

µs

µA

pF

V

ms

V

DD

Supply Current

I

DD

CE = V

DD

(Note 7)

CE = GND

AVDD Supply Range

AVDD Supply Current

CTL High Voltage

CTL Low Voltage

CTL High Rejected Pulse Width

CTL Low Rejected Pulse Width

CTL High Minimum Pulse Width

CTL Low Minimum Pulse Width

CTL Minimum Time Between

Counts

CTL Input Current

AVDD

IAVDD

CTL

IH

CTL

IL

CTL

IHRPW

CTL

ILRPW

CTL

IHMPW

CTL

ILMPW

CTL

MTC

ICTL

CTL = GND

CTL = V

DD

(Note 4)

2.6V < V

DD

< 3.6V

2.6V < V

DD

< 3.6V

Full

CTL Input Capacitance

CE Input Low Voltage

CE Input High Voltage

CE Minimum Start-Up Time

CTL EEPROM Program Voltage

CTL

CAP

CE

IL

CE

IH

CE

ST

CTL

PROM

(Note 6)

2.6V < V

DD

< 3.6V

2.6V < V

DD

< 3.6V

(Note 6)

2.6V < V

DD

< 3.6V, (Note 3)

FN6158 Rev 4.00

Jul 9, 2008

Page 3 of 8

ISL45042A

Electrical Specifications

Test Conditions: V

DD

= 3V, AV

DD

= 10V, OUT = 5V, R

SET

= 24.9k; Unless Otherwise Specified.

Typicals are at T

A

= +25°C

(Continued)

SYMBOL

CTL

PT

P

T

SET

VR

SET

DN

SET

ZSE

SET

FSE

ISET

SET

ER

Through R

SET

(Note 8)

To GND, AVDD = 20V

To GND, AVDD = 4.5V

AVDD to SET Voltage Attenuation

OUT Settling Time

OUT Voltage Range

OUT Voltage Drift

NOTES:

3. CTL signal only needs to be greater than 4.9V to program EEPROM.

4. Tested at AV

DD

= 20V.

5. The Counter value is set to mid-scale ±4 LSB’s in the Production.

6. Simulated and Determined via Design and NOT Directly Tested.

7. Simulated Maximum Current Draw when Programming EEPROM is 23mA; should be considered when designing Power Supply.

8. A Typical Current of 20µA is Calculated using the AV

DD

= 10V and R

SET

= 24.9k. Reference “RSET Resistor” on page 6.

9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

AVDD to SET

OUT

ST

V

OUT

VD

(Note 6)

to ±0.5 LSB Error Band (Note 6)

(Note 5)

Monotonic Over-Temperature

>4.9V

TEST CONDITIONS

TEMP

(°C)

Full

25 to 55

MIN

(Note 9)

200

-

7

-

10

2.25

-

VSET + 0.5V

-

TYP

-

7

-

20

-

1:20

20

-

<10

MAX

(Note 9) UNITS

-

100

7

±1

±2

±8

-

200

45

-

13

-

µs

ms

Bits

LSB

µA

k

V/V

µs

V

mV

PARAMETER

CTL EEPROM Programming

Signal Time

Programming Time

SET Voltage Resolution

SET Differential Nonlinearity

SET Zero-Scale Error

SET Full-Scale Error

SET Current

SET External Resistance

Application Information

AVDD

ISL45042A

CTL

CE

SET

R

SET

VCOM

+

-

GREEN

BLUE

RED

OUT

R

2

I

SINK

AVDD

R

1

The application circuit to adjust the V

COM

voltage in an LCD

panel is shown in Figure 1. The ISL45042A has a 128-step

sink current resolution. The output is connected to an

external voltage divider, that results in decreasing the output

V

COM

voltage as you increase the ISL45042A sink current.

CTL Pin

The adjustment of the output V

COM

voltage and the

programming of the non-volatile memory are provided

through a single pin called CTL when the CE pin is high.

The output V

COM

voltage is increased with a mid (V

DD

/2) to

high transition (0.8*V

DD

) on the CTL pin. The output V

COM

voltage is decreased with a mid (V

DD

/2) to low transition

(0.3*V

DD

) on the CTL pin (see Figure 7). Once the minimum

or maximum value is reached on the 128 steps, the device

will not overflow or underflow beyond that minimum or

maximum value.

Programming of the non-volatile memory occurs when the

CTL pin exceeds 4.9V. The CTL signal needs to remain

above 4.9V for more than 200µs. The level and timing

COLUMN

DRIVER

SINGLE PIXEL

IN LCD PANEL

FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL

FN6158 Rev 4.00

Jul 9, 2008

Page 4 of 8

ISL45042A

needed to program the non-volatile memory is given in

Figure 2. It then takes a maximum of 100ms for the

programming to be completed inside the device.

CTL VOLTAGE

>200µs

4.9V

CE Pin

To adjust the output voltage, the CE pin must be pulled high

(VDD). The CE pin has an internal pull-down resistor to

prevent unwanted reprogramming of the EEPROM. The

impedance of this resistor is 400k to 500k (see

R

INTERNAL

in Figure 6).

The CE pin has a Schmitt trigger on the input to prevent

false triggering during slow transitions of the CE pin.

Transitions of the CE pin are recommended to be less than

10µs.

CTL

PT

TIME

Replacing Existing Mechanical Potentiometer

Circuits

Figure 4 shows the common adjustment mechanical circuits

and equivalent replacement with the ISL45042A.

FIGURE 2. EEPROM PROGRAMMING

When the part is programmed, the counter setting is loaded

into the non-volatile memory. This value will be loaded from

the nonvolatile memory during initial power-up or when the

CE pin is pulled low.

Once the programming is completed, it is recommended that

the user float the CLT pin. The CTL pin is internally tied to a

resistor network connected to ground. If left floating, the

voltage at the CTL pin will equal V

DD

/2. Under these

conditions, no additional pulses will be seen by the Up/Down

counter via the CTL pin. To prevent further programming,

ground the CE pin.

CTL should have a noise filter to reduce bouncing or noise

on the input that could cause unwanted counting when the

CE pin is high. The board should have an additional ESD

protection circuit, with a series 1k resistor and a shunt

0.01µF capacitor connected on the CTL pin, (see Figure 3).

To avoid unintentional adjustment, the ISL45042A

guarantees to reject CTL pulses shorter than 20µs.

During Initial Power-up (only), to avoid the possibility of a

false pulse (since the internal comparators come up in an

unknown state), the very first CTL pulse is ignored. See

Figure 7 for the timing information.

AVDD

R

a

VCOM

Expected Output Voltage

The ISL45042A provides an output sink current, which

lowers the voltage on the external voltage divider (V

COM

output voltage). Equations 1 and 2 can be used to calculate

the output current (I

OUT

) and output voltage (V

OUT

) values.

AV

DD

Setting

-

I

OUT

= --------------------

x

--------------------------

20



R

SET



128

R

1



R

2







Setting

-

V

OUT

=



--------------------



AV

DD



1

– --------------------

x

--------------------------



20



R

SET



128



R

1

+

R

2





NOTE: Where setting is an integer between 1 and 128.

(EQ. 1)

(EQ. 2)

1k

0.01µF

ISL45042A

CTL

FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN

AVDD

-

+

ISL45042A

OUT

AVDD

R

1

-

+

R

2

R

b

VCOM

SET

R

c

R

1

= R

a

R

2

= R

b

+ R

c

R

SET

= (R

a

(R

b

+ Rc)) / 20R

b

R

SET

FIGURE 4. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042A

FN6158 Rev 4.00

Jul 9, 2008

Page 5 of 8

ISL45042AIRZ-TK

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