CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, R
SET
= 24.9kΩ; Unless Otherwise Specified.
Typicals are at T
A
= +25°C
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
PARAMETER
DC CHARACTERISTICS
V
DD
Supply Range
V
DD
For Programming
For Operation
0 to 85
Full
Full
Full
Full
3
2.6
-
-
4.5
-
0.7*V
DD
0.2*V
DD
20
20
-
-
-
-
-
-
-
0.64*V
DD
-
4.9
200
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
-
-
1
-
-
3.6
3.6
50
20
20
20
0.8*V
DD
0.3*V
DD
-
-
200
200
10
10
10
-
0.4
-
-
15.75
-
V
V
μA
μA
V
μA
V
V
μs
μs
μs
μs
μs
μA
μA
pF
V
V
ms
V
μs
V
DD
Supply Current
I
DD
CE = V
DD
(Note 6)
CE = GND
AVDD Supply Range
AVDD Supply Current
CTL High Voltage
CTL Low Voltage
CTL High Rejected Pulse Width
CTL Low Rejected Pulse Width
CTL High Minimum Pulse Width
CTL Low Minimum Pulse Width
CTL Minimum Time Between
Counts
CTL Input Current
AVDD
IAVDD
CTL
IH
CTL
IL
CTL
IHRPW
CTL
ILRPW
CTL
IHMPW
CTL
ILMPW
CTL
MTC
ICTL
CTL = GND
CTL = V
DD
(Note 3)
2.6V < V
DD
< 3.6V
2.6V < V
DD
< 3.6V
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
CTL Input Capacitance
CE Input Low Voltage
CE Input High Voltage
CE Minimum Start Up Time
CTL EEPROM Program Voltage
CTL EEPROM Programming
Signal Time
CTL
CAP
CE
IL
CE
IH
CE
ST
CTL
PROM
CTL
PT
(Note 5)
2.6V < V
DD
< 3.6V
2.6V < V
DD
< 3.6V
(Note 5)
2.6V < V
DD
< 3.6V, (Note 2)
>4.9V
3
FN6072.6
November 14, 2006
ISL45042
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, R
SET
= 24.9kΩ; Unless Otherwise Specified.
Typicals are at T
A
= +25°C
(Continued)
SYMBOL
P
T
SET
VR
SET
DN
SET
ZSE
SET
FSE
ISET
SET
ER
Through R
SET
(Note 7)
To GND, AVDD = 20V
To GND, AVDD = 4.5V
AVDD to SET Voltage Attenuation
OUT Settling Time
OUT Voltage Range
OUT Voltage Drift
NOTES:
2. CTL signal only needs to be greater than 4.9V to program EEPROM.
3. Tested at AVDD = 20V.
4. The Counter value is set to mid-scale
±4
LSB’s in the Production.
5. Simulated and Determined via Design and NOT Directly Tested.
6. Simulated Maximum Current Draw when Programming EEPROM is 23mA, should be considered when designing Power Supply.
7. A Typical Current of 20μA is Calculated using the AVDD = 10V and RSET = 24.9kΩ. The maximum suggested SET Current should be 120μA.
AVDD to SET
OUT
ST
V
OUT
OUT
VD
(Note 5)
to
±0.5
LSB Error Band (Note 5)
(Note 4)
Monotonic Over Temperature
TEST CONDITIONS
TEMP
(°C)
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25 to 55
7
-
-
-
-
10
2.25
-
-
VSET +
0.5V
-
7
-
-
-
20
-
-
1:20
20
-
<10
MIN
TYP
MAX
100
7
±1
±2
±8
-
200
45
-
-
13
-
UNITS
ms
Bits
LSB
LSB
LSB
μA
kΩ
kΩ
V/V
μs
V
mV
PARAMETER
Programming Time
SET Voltage Resolution
SET Differential Nonlinearity
SET Zero-Scale Error
SET Full-Scale Error
SET Current
SET External Resistance
Application Information
The application circuit to adjust the VCOM voltage in an LCD
panel is shown in Figure 1. The ISL45042 has a 128-step
sink current resolution. The output is connected to an
external voltage divider, that results in decreasing the output
VCOM voltage as you increase the ISL45042 sink current.
AVDD
ISL45042
CTL
CE
OUT
SET
R
SET
I
Sink
AVDD
R
1
R
2
CTL Pin
The adjustment of the output VCOM voltage and the
programming of the non-volatile memory are provided
through a single pin called CTL, when the CE pin is high.
The output VCOM voltage is increased with a mid (Vdd/2) to
high transition (0.8*VDD) on CTL pin. The output VCOM
voltage is decreased with a mid (Vdd/2) to low transition
(0.3*VDD), on CTL pin (Reference Figure 6). Once the
minimum or maximum value is reached on the 128 steps,
the device will not overflow or underflow beyond that
minimum or maximum value.
Programming of the non-volatile memory occurs when the
CTL pin exceeds 4.9V. The CTL signal needs to remain
above 4.9V for more than 200µs. The level and timing
needed to program the non-volatile memory is given in
Figure 2. It then takes a maximum of 100ms for the
programming to be completed inside the device.
VCOM
+
-
GREEN
COLUMN
DRIVER
SINGLE PIXEL
IN LCD PANEL
FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL
4
BLUE
FN6072.6
November 14, 2006
RED
ISL45042
CTL VOLTAGE
>200µs
To avoid unintentional adjustment, the ISL45042 guarantees
to reject CTL pulses shorter than 20µs.
During Initial Power-up (only), to avoid the possibility of a
false pulse (since the internal comparators come up in an
unknown state) the very first CTL pulse is ignored. See
Figure 6 for the timing information.
4.9V
CE Pin
CTL
PT
TIME
FIGURE 2. EEPROM PROGRAMMING
When the part is programmed, the counter setting is loaded
into the non-volatile memory. This value will be loaded from
the nonvolatile memory during initial power-up or when the
CE pin is pulled low.
Once the programming is completed it is recommended that
the user float the CLT pin. The CTL pin is internally tied to a
resistor network connected to ground. If left floating, the
voltage at the CTL pin will equal V
DD
/2. Under these
conditions, no additional pulses will be seen by the Up/Down
counter via the CTL pin. To prevent further programming
ground the CE pin.
CTL should have a noise filter to reduce bouncing or noise
on the input that could cause unwanted counting when the
CE pin is high. The board should have an additional ESD
protection circuit, with a series 1kΩ resistor and a shunt
0.01µF capacitor connected on the CTL pin. (See Figure 3)
1kΩ
To adjust the output voltage, the CE pin must be pulled high
(VDD). The CE pin has an internal pull-down resistor to
prevent unwanted reprogramming of the EEPROM. The
impedance of this resistor is 400kΩ to 500kΩ (R
INTERNAL
Figure 5).
Transitions of the CE pin are recommended to be less than
10μ seconds.
Replacing Existing Mechanical Potentiometer
Circuits
Figure 4 shows the common adjustment mechanical circuits
and equivalent replacement with the ISL45042.
Expected Output Voltage
The ISL45042 provides an output sink current which lowers
the voltage on the external voltage divider (VCOM output
voltage). EQ. 1 and EQ. 2 can be used to calculate the
output current (IOUT) and output voltage (VOUT) values.
Setting
AVDD
-
-
IOUT
= --------------------
X
----------------------------
128
20
(
RSET
)
(EQ. 1)
ISL45042
CTL
R2
-
Setting
R1
-
-
VOUT
=
⎛
---------------------
⎞
AVDD
⎛
1
– --------------------
X
----------------------------
⎞
⎝
R1
+
R2
⎠
⎝
128
20
(
RSET
)⎠
(EQ. 2)
0.01µF
NOTE: Where setting is an integer between 1 and 128.
FIGURE 3. EXTERNAL ESD PROTECTION ON CTL PIN
AVDD
R
a
VCOM
R
b
-
+
ISL45042
OUT
R
2
R
1
-
+
VCOM
AVDD
AVDD
SET
R
c
R
1
= Ra
R
2
= Rb + Rc
R
SET
= (Ra(Rb + Rc)) / 20Rb
R
SET
FIGURE 4. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE ISL45042
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