®
EL7535
Data Sheet
July 13, 2006
FN7003.5
Monolithic 350mA Step-Down Regulator
The EL7535 is a synchronous, integrated FET 350mA step-
down regulator in a MSOP10 package. The regulator is
internally compensated, which makes it possible to use just
five tiny external components to form a complete DC/DC
converter. The regulator operates with an input voltage
range from 2.5V to 6V, which accommodates supplies of
3.3V, 5V, or a Li-Ion battery source. The output can be
externally set from 0.8V to V
IN
with a resistive divider.
The EL7535 features PWM mode control. The operating
frequency is typically 1.4MHz. Additional features include
<1µA shut-down current, short-circuit protection, and over-
temperature protection.
The EL7535 is available in the 10 Ld MSOP package and is
specified for operation over the full -40°C to +85°C
temperature range.
Features
• Extremely small 350mA DC/DC converter
• Max height 1.1mm MSOP10 package
• Possibly uses only five tiny external components with fixed
output
• Power-On-Reset output (POR)
• Internally-compensated voltage mode controller
• Up to 94% efficiency
• <1µA shut-down current
• Overcurrent and over-temperature protection
• Pb-free plus anneal available (RoHS compliant)
Applications
• PDA and pocket PC computers
• Bar code readers
Ordering Information
PART NUMBER
PART
TAPE &
(BRAND)
MARKING REEL
EL7535IY
EL7535IY-T7
EL7535IY-T13
EL7535IYZ
(Note)
EL7535IYZ-T7
(Note)
a
a
a
BAACA
BAACA
-
7”
13”
-
7”
13”
PACKAGE
10 Ld MSOP
10 Ld MSOP
10 Ld MSOP
10 Ld MSOP
(Pb-free)
10 Ld MSOP
(Pb-free)
10 Ld MSOP
(Pb-free)
PKG.
DWG. #
MDP0043
MDP0043
MDP0043
MDP0043
MDP0043
MDP0043
• Cellular phones
• Portable test equipment
• Li-Ion battery powered devices
• Small form factor (SFP) modules
Typical Application Diagram
EL7535
(10 LD MSOP)
TOP VIEW
V
S
(2.5V to 5.5V)
VIN
R
3
100Ω
C
2
10µF
C
3
0.1µF
R
5
100kΩ
POR
EN
FB
R
2
*
100kΩ
VO
R
4
100kΩ
R
6
100kΩ
VDD
EL7535
EL7535IYZ-T13 BAACA
(Note)
LX
L
1
1.8µH
C
1
10µF
V
O
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
R
1
*
124kΩ
C
4
470pF
Pinout
EL7535 (10 LD MSOP)
TOP VIEW
1
SGND
2
PGND
3
LX
4
VIN
5
VDD
FB
10
VO
9
POR
8
EN
7
RSI
6
RSI
PGND
SGND
(1.8V @ 350mA)
* V
O
= 0.8V * (1 + R
1
/ R
2
)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL7535
Absolute Maximum Ratings
(T
A
= 25°C)
V
IN
, V
DD
, POR to SGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V
IN
+ +0.3V)
RSI, EN, V
O
, FB to SGND . . . . . . . . . . . . . . . -0.3V to (V
IN
+ +0.3V)
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
DC CHARACTERISTICS
V
FB
I
FB
V
IN
, V
DD
V
IN,OFF
V
IN,ON
I
DD
V
DD
= V
IN
= V
EN
= 3.3V, C1 = C2 = 10µF, L = 1.8µH, V
O
= 1.8V, unless otherwise specified.
CONDITIONS
MIN
TYP
MAX
UNIT
DESCRIPTION
Feedback Input Voltage
Feedback Input Current
Input Voltage
Minimum Voltage for Shutdown
Maximum Voltage for Startup
Supply Current
V
IN
falling
V
IN
rising
PWM, V
IN
= V
DD
= 5V
EN = 0, V
IN
= V
DD
= 5V
790
800
810
250
mV
nA
V
V
V
µA
µA
mΩ
mΩ
A
°C
°C
2.5
2
2.2
400
0.1
70
45
1.5
T rising
T falling
V
EN
, V
RSI
= 0V and 3.3V
V
DD
= 3.3V
V
DD
= 3.3V
V
FB
rising
V
FB
falling
I
SINK
= 5mA
86
35
0.8
-1
145
130
6
2.2
2.4
500
1
100
75
R
DS(ON)-PMOS
PMOS FET Resistance
V
DD
= 5V, wafer test only
V
DD
= 5V, wafer test only
R
DS(ON)-NMOS
NMOS FET Resistance
I
LMAX
T
OT,OFF
T
OT,ON
I
EN
, I
RSI
V
EN1
, V
RSI1
V
EN2
, V
RSI2
V
POR
Current Limit
Over-temperature Threshold
Over-temperature Hysteresis
EN, RSI Current
EN, RSI Rising Threshold
EN, RSI Falling Threshold
Minimum V
FB
for POR, WRT Targeted
V
FB
Value
POR Voltage Drop
1
2.4
µA
V
V
95
%
%
V
OLPOR
70
mV
AC CHARACTERISTICS
F
PWM
t
RSI
t
SS
t
POR
PWM Switching Frequency
Minimum RSI Pulse Width
Soft-start Time
Power On Reset Delay Time
80
Guaranteed by design
1.25
1.4
25
650
100
120
1.55
50
MHz
ns
µs
ms
2
FN7003.5
July 13, 2006
EL7535
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
PIN NAME
SGND
PGND
LX
VIN
VDD
RSI
EN
POR
VO
FB
Negative supply for the controller stage
Negative supply for the power stage
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage
Positive supply for the power stage
Power supply for the controller stage
Resets POR timer
Enable
Power on reset open drain output
Output voltage sense
Voltage feedback input; connected to an external resistor divider between V
O
and SGND for variable
output
PIN FUNCTION
Timing Diagram
V
O
MIN
25ns
RSI
100ms
POR
100ms
3
FN7003.5
July 13, 2006
EL7535
Typical Performance Curves
100
95
90
EFFICIENCY (%)
85
80
75
70
65
60
0
100
200
I
O
(mA)
300
400
V
O
=1.2V
V
O
=1.8V
V
O
=2.5V
EFFICIENCY (%)
100
V
O
=3.3V
95
90
85
80
75
70
65
60
0
100
200
I
O
(mA)
300
400
V
O
=1V
V
O
=1.8V
V
O
=1.2V
V
IN
=5V
V
IN
=3.3V
V
O
=2.5V
FIGURE 1. EFFICIENCY
FIGURE 2. EFFICIENCY
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
0
P1
/W
°C
SO
M 115
=
θ
J
A
ALLOWABLE POWER DISSIPATION (W)
0.6
0.5
0.4
0.3
0.2
0.1
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
θ
M
SO
JA
P
=2
06 10
°C
/W
FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 4. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Waveforms
All waveforms are taken at V
IN
= 3.3V, V
O
= 1.8V, I
O
= 350mA with component values shown on page 1, unless otherwise noted
V
IN
(2V/DIV)
V
IN
(1V/DIV)
I
IN
(0.2A/DIV)
V
O
(1V/DIV)
ALLOWABLE POWER DISSIPATION (W)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
V
O
(2V/DIV)
POR
(2V/DIV)
0.5ms/DIV
50ms/DIV
FIGURE 5. START-UP 1
FIGURE 6. START-UP 2
5
FN7003.5
July 13, 2006
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