IS64LF6432-8.5TQA1 datasheet, PDF

IS64LF6436

IS64LF6432

64K x 32, 64Kx36 SYNCHRONOUS

FLOW-THROUGH STATIC RAM

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Interleaved or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 100-Pin TQFP package

• Power Supply:

+3.3V V

DD

+3.3V or 2.5V V

DDQ

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

• Temperature offerings:

Option A1: -40

0

C to +85

0

C

Option A2: -40

0

C to +105

0

C

Option A3: -40

0

C to +125

0

C

ISSI

PRELIMINARY INFORMATION

AUGUST 2003

®

DESCRIPTION

The

ISSI

IS64LF6432 and IS64LF6436 are high-speed,

low-power synchronous static RAM designed to provide a

burstable, high-performance, memory. IS64LF6432 is orga-

nized as 65,536 words by 32 bits and IS64LF6436 is

organized as 65,536 words by 36 bits. They are fabricated

with

ISSI

's advanced CMOS technology. The device inte-

grates a 2-bit burst counter, high-speed SRAM core, and

high-drive capability outputs into a single monolithic circuit.

All synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1

controls DQ1-DQ8,

BW2

controls DQ9-DQ16,

BW3

controls DQ17-DQ24,

BW4

controls DQ25-DQ32, condi-

tioned by

BWE

being LOW. A LOW on

GW

input would

cause all bytes to be written.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally by the IS64LF6432/36 and controlled by the

ADV

(burst address advance) input pin.

The mode pin is used to select the burst sequence order.

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

t

KQ

t

KC

Parameter

Clock Access Time

Cycle Time

Frequency

8.5

11

90

10

15

66

Unit

ns

MHz

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00B

07/24/03

1

IS64LF6432

IS64LF6436

ISSI

MODE

Q0

A0'

A0

Q1

A1'

A1

®

BLOCK DIAGRAM

CLK

BINARY

COUNTER

ADV

ADSC

ADSP

CE

CLR

64Kx32 / 64Kx36

MEMORY

ARRAY

14

16

A

16

D

Q

ADDRESS

REGISTER

CE

CLK

32

or

36

32

or

36

GW

BWE

BW4

(x32/x36)

D

Q

DQ32-DQ25

BYTE WRITE

REGISTERS

CLK

D

BW3

(x32/x36)

Q

DQ24-DQ17

BYTE WRITE

REGISTERS

CLK

D

BW2

(x32/x36)

Q

DQ16-DQ9

BYTE WRITE

REGISTERS

CLK

D

BW1

(x32/x36)

Q

DQ8-DQ1

BYTE WRITE

REGISTERS

CLK

CE

CE2

D

Q

4

ENABLE

REGISTER

CE

CLK

INPUT

REGISTERS

CLK

OE

32 or 36

DATA[32:1]

D

Q

ENABLE

DELAY

REGISTER

CLK

OE

2

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00B

07/24/03

IS64LF6432

IS64LF6436

ISSI

®

PIN CONFIGURATION

100-Pin TQFP

A

CE

CE2

BW4

BW3

BW2

BW1

CE2

VDD

GND

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

2

79

3

78

4

77

5

76

6

75

7

74

8

73

9

72

10

71

11

70

12

69

13

68

14

67

15

66

16

65

17

64

18

63

19

62

20

61

21

60

22

59

23

58

24

57

25

56

26

55

27

54

28

53

29

52

30

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC

DQc

VDDQ

GND

DQc

GND

VDDQ

DQc

NC

VDD

NC

GND

DQd

VDDQ

GND

DQd

GND

VDDQ

DQd

NC

DQb

VDDQ

GND

DQb

GND

VDDQ

DQb

GND

NC

VDD

ZZ

DQa

VDDQ

GND

DQa

GND

VDDQ

DQa

NC

64K x 32

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These

pins must tied to the two LSBs of the

address bus.

Synchronous Address Inputs

Synchronous Clock

Synchronous Processor Address

Status

Synchronous Controller Address

Status

Synchronous Burst Address Advance

Individual Byte Write Enable

Synchronous Byte Write Enable

GW

CE, CE2,

CE2

OE

DQa-DQd

MODE

V

DD

GND

V

DDQ

ZZ

Synchronous Global Write Enable

Synchronous Chip Enable

Output Enable

Synchronous Data Input/Output

Burst Sequence Mode Selection

+3.3V Power Supply

Ground

Isolated Output Buffer Supply: +3.3V

or 2.5V

Snooze Enable

A

CLK

ADSP

ADSC

ADV

BW1-BW4

BWE

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00B

07/24/03

MODE

A

A1

A0

NC

GND

VDD

NC

A

NC

3

IS64LF6432

IS64LF6436

ISSI

®

PIN CONFIGURATION

100-Pin TQFP

A

CE

CE2

BW4

BW3

BW2

BW1

CE2

VDD

GND

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

DQPc

DQc

VDDQ

GND

DQc

GND

VDDQ

DQc

NC

VDD

NC

GND

DQd

VDDQ

GND

DQd

GND

VDDQ

DQd

DQPd

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

2

79

3

78

4

77

5

76

6

75

7

74

8

73

9

72

10

71

11

70

12

69

13

68

14

67

15

66

16

65

17

64

18

63

19

62

20

61

21

60

22

59

23

58

24

57

25

56

26

55

27

54

28

53

29

52

30

51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

MODE

A

A1

A0

NC

GND

VDD

NC

A

NC

DQPb

DQb

VDDQ

GND

DQb

GND

VDDQ

DQb

GND

NC

VDD

ZZ

DQa

VDDQ

GND

DQa

GND

VDDQ

DQa

DQPa

64K x 36

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These

pins must tied to the two LSBs of the

address bus.

Synchronous Address Inputs

Synchronous Clock

Synchronous Processor Address

Status

Synchronous Controller Address

Status

Synchronous Burst Address Advance

Individual Byte Write Enable

Synchronous Byte Write Enable

GW

CE, CE2,

CE2

OE

DQa-DQd

MODE

V

DD

GND

V

DDQ

ZZ

DQPa-DQPd

Synchronous Global Write Enable

Synchronous Chip Enable

Output Enable

Synchronous Data Input/Output

Burst Sequence Mode Selection

+3.3V Power Supply

Ground

Isolated Output Buffer Supply: +3.3V or

2.5V

Snooze Enable

Parity Data I/O

A

CLK

ADSP

ADSC

ADV

BW1-BW4

BWE

4

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00B

07/24/03

IS64LF6432

TRUTH TABLE

Operation

IS64LF6436

ISSI

CE2

X

L

X

L

H

X

CE2

X

H

X

H

X

L

X

ADSP ADSC

X

L

H

L

H

X

H

X

H

X

H

X

L

X

L

X

L

H

ADV

X

L

H

WRITE

X

Read

Write

Read

Write

Read

Write

OE

X

L

H

L

H

X

L

H

L

H

X

DQ

High-Z

Q

D

Q

High-Z

Q

High-Z

D

Q

High-Z

Q

High-Z

D

H

L

X

L

X

H

X

H

X

H

X

H

®

Address

Used

CE

None

External

Current

Deselected, Power-down

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

PARTIAL TRUTH TABLE

Function

Read

Write Byte 1

Write All Bytes

GW

H

L

BWE

H

L

X

BW1

X

H

L

X

BW2

X

H

L

X

BW3

X

H

L

X

BW4

X

H

L

X

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. 00B

07/24/03

5

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	8.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	2097152 bit
Memory IC Type	CACHE SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64KX32
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

	IS64LF6432-8.5TQA1	IS64LF6436-8.5TQA1
Description	Cache SRAM, 64KX32, 8.5ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 64KX36, 8.5ns, CMOS, PQFP100, TQFP-100
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	QFP	QFP
package instruction	TQFP-100	TQFP-100
Contacts	100	100
Reach Compliance Code	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A
Maximum access time	8.5 ns	8.5 ns
Other features	FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PQFP-G100	R-PQFP-G100
JESD-609 code	e0	e0
length	20 mm	20 mm
memory density	2097152 bit	2359296 bit
Memory IC Type	CACHE SRAM	CACHE SRAM
memory width	32	36
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	100	100
word count	65536 words	65536 words
character code	64000	64000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	64KX32	64KX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP
Package shape	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	240	240
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.63 V	3.63 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	30	30
width	14 mm	14 mm
Base Number Matches	1	1

IS64LF6432-8.5TQA1

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