UTC 4053
ANALOG MULTIPLEXERS/ DEMULTIPLEXERS
DESCRIPTION
The UTC
4053 are
Triple SPDT analog multiplexers for
application as digitally–controlled analog switches.
CMOS IC
SOP-16
FEATURES
* Analog Voltage Range (V
DD
– V
EE
) = 3.0 ~ 18 V
Note: V
EE
must be≦V
SS
* Linearized Transfer Characteristics
* Pin–to–Pin Replacement for CD4053
DIP-16
TSSOP-16
*Pb-free plating product number: 4053L
PIN CONFIGURATIONS
Y
1
Y
0
Z
1
Z
Z
0
INH
V
EE
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Y
X
X
1
X
0
A
B
C
UTC 4053
UTC
UNISONIC TECHNOLOGIES
CO., LTD.
1
QW-R502-036,A
www.unisonic.com.tw
UTC 4053
UTC 4053 Triple 2–Channel Analog Multiplexer/Demultiplexer
6
11
10
9
12
13
2
1
5
3
INHIBIT
X
A
B
C
X0
Y
X1
Y0
Y1
Z
Z0
Z1
V
DD
= PIN 16
V
SS
= PIN 8
V
EE
= PIN 7
CMOS IC
CONTROLS
14
15
COMMONS
OUT/IN
SWITCHES
IN/OUT
4
Note: Control Inputs referenced to V
SS
, Analog Inputs and Outputs reference to V
EE
. V
EE
must be
≦
V
SS
.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
DC Supply Voltage (Referenced to V
EE
, V
SS
≧
V
EE
)
SYMBOL
V
DD
RATINGS
-0.5 ~ +18.0
-0.5 ~ V
DD
+0.5
±10
±25
500
-65 ~ +150
260
UNIT
V
V
mA
mA
mW
℃
℃
Input or Output Voltage (DC or Transient) (Referenced to V
SS
V
in
, V
out
for Control Inputs and V
EE
for Switch I/O)
Input Current (DC or Transient), per Control Pin
I
in
Switch Through Current
I
SW
Power Dissipation. Per Package**
P
D
Storage Temperature
T
stg
Lead Temperature (8 - Second Soldering)
T
Lead
* Maximum Ratings are those values beyond which damage to the device may occur.
** Temperature Derating: “DIP and SOP” Packages: – 7.0 mW/
℃
From 65
℃
~ 125
℃
ELECTRICAL CHARACTERISTICS
(Ta=25
℃
, unless otherwise indicated.)
PARAMETER
SYMBOL
TEST CONDITIONS
SUPPLY REQUIREMENTS (Voltages Referenced to V
EE
)
V
DD
– 3.0
≧
V
SS
≧
V
EE
Power Supply Voltage Range
V
DD
MIN
3.0
TYP#
MAX
18
UNIT
V
Quiescent Current per Package
I
DD
Total Supply Current (Dynamic Plus
Quiescent, Per Package)
I
D(AV)
Control Inputs: Vin = V
SS
or V
DD
Switch I/O: V
EE
≦
V
I/O
≦
V
DD
,
and
∆Vswitch
≦
500mV*
V
DD
=5.0V
0.005
5.0
V
DD
=10V
0.010
10
V
DD
=15V
0.015
20
T
a
=25
℃
only (The channel
component, (Vin - Vout)/Ron, is
not included.)
V
DD
=5.0V
(0.07 µA/kHz) f + I
DD
Typical
V
DD
=10V
(0.20 µA/kHz) f + I
DD
V
DD
=15V
(0.36 µA/kHz) f + I
DD
µA
µA
UTC
UNISONIC TECHNOLOGIES
CO., LTD.
2
QW-R502-036,A
www.unisonic.com.tw
UTC 4053
CMOS IC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP#
MAX UNIT
CONTROL INPUTS – INHIBIT A, B, C (Voltages Referenced to V
SS
)
Ron= per spec, Ioff = per spec
V
DD
=5.0V
2.25
1.5
Low – Level Input Voltage
V
IL
V
V
DD
=10V
4.50
3.0
V
DD
=15V
6.75
4.0
Ron= per spec, Ioff = per spec
V
DD
=5.0V
3.5
2.75
High – Level Input Voltage
V
IH
V
V
DD
=10V
7.0
5.50
V
DD
=15V
11
8.25
Input Leakage Current
Iin
Vin= 0 or V
DD
, V
DD
=15V
±0.00001 ±0.1
µA
Input Capacitance
Cin
5.0
7.5
pF
SWITCHES IN/OUT AND COMMONS OUT/IN -- X, Y, Z (Voltages Referenced to V
EE
)
Recommended Peak–to–Peak Voltage
Channel On or Off
V
I/O
0
V
DD
V
PP
Into or Out of the Switch
Recommended Static or Dynamic
Channel On
∆Vswitch
0
600
mV
Voltage Across the Switch** (Figure 3)
Output Offset Voltage
V
OO
Vin = 0V, No Load
10
µV
∆Vswitch
≦
500mV*
Vin = V
IL
or V
IH
(Control), and
Vin = 0 to V
DD
(Switch)
ON Resistance
Ron
Ω
V
DD
=5.0V
250
1050
V
DD
=10V
120
500
V
DD
=15V
80
280
V
DD
=5.0V
25
70
Δ
ON Resistance Between Any Two
∆Ron
V
DD
=10V
10
50
Ω
Channels in the Same Package
V
DD
=15V
10
45
Vin = V
IL
or V
IH
(Control)
Off–Channel Leakage Current
Channel to Channel or Any
Ioff
±0.05
±100
nA
(Figure 8)
One Channel, V
DD
=15V
Capacitance, Switch I/O
C
I/O
Inhibit = V
DD
10
pF
Capacitance, Common O/I
C
O/I
Inhibit = V
DD
17
pF
Capacitance, Feedthrough
Pins Not Adjacent
0.15
C
I/O
pF
(Channel Off)
Pins Adjacent
0.47
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential
performance.
* For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive V
DD
current may
be drawn, i.e. the current out of the switch may contain both V
DD
and switch input components. The reliability of the
device will be unaffected unless the Maximum Ratings are exceeded. (See second page of this data sheet.)
UTC
UNISONIC TECHNOLOGIES
CO., LTD.
3
QW-R502-036,A
www.unisonic.com.tw
UTC 4053
ELECTRICAL CHARACTERISTICS*
(C
L
= 50pF, T
a
=25
℃
, V
EE
≦
V
SS
, unless otherwise indicated.)
PARAMETER
SYMBOL V
DD
– V
EE
Vdc
Propagation Delay Times
5.0
(Figure 4) Switch Input to
10
t
PLH,
t
PHL
Switch Output (R
L
= 10 kΩ)
15
5.0
t
PHZ,
t
PLZ
Inhibit to Output
10
t
PZH,
t
PZL
15
Control Input to Output
5.0
t
PLH,
t
PHL
10
15
Second Harmonic Distortion
10
CMOS IC
TEST CONDITIONS
MIN TYP# MAX UNIT
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 16.5 ns
25
65
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 4.0 ns
8.0
20
ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 3.0 ns
6.0
15
275
550
(R
L
=10kΩ, V
EE
=V
SS
)Output “1” or “0”
to High Impedance, or High
140
280
ns
Impedance to “1” or “0” Level
110
220
300
600
R
L
= 10 kΩ, V
EE
= V
SS
120
240
ns
80
160
R
L
= 10KΩ, f = 1 kHz, Vin = 5 V
PP
0.07
%
R
L
= 1kΩ, Vin = 1/2 (V
DD
–V
EE
) p–p,
Bandwidth (Figure 5)
BW
10
17
MHz
C
L
= 50pF, 20 Log (Vout/Vin) = -3dB)
Off Channel Feedthrough
R
L
= 1KΩ, Vin = 1/2 (V
DD
– V
EE
) p–p
10
-50
dB
Attenuation (Figure 5)
fin = 55 MHz
Channel Separation
R
L
= 1 kΩ, Vin = 1/2 (V
DD
–V
EE
) p–p
10
-50
dB
(Figure 6)
fin = 3.0 MHz
Crosstalk, Control Input to
R
1
= 1 kΩ, R
L
= 10 kΩ Control
10
75
mV
Common O/I (Figure 7)
t
TLH
= t
THL
= 20 ns, Inhibit = V
SS
)
* The formulas given are for the typical characteristics only at 25
℃
.
# Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential
performance.
V
DD
IN/OUT
V
DD
V
DD
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
V
EE
CONTROL
Figure 1. Switch Circuit Schematic
UTC
UNISONIC TECHNOLOGIES
CO., LTD.
4
QW-R502-036,A
www.unisonic.com.tw
UTC 4053
TRUTH TABLE
Control Inputs
Select
Inhibit
C B A
0
0 0 0
0
0 0 1
0
0 1 0
0
0 1 1
0
1 0 0
0
1 0 1
0
1 1 0
0
1 1 1
1
x x x
x = Don’t Care
ON Switches
UTC 4053
Z0 Y0 X0
Z0 Y0 X1
Z0 Y1 X0
Z0 Y1 X1
Z1 Y0 X0
Z1 Y0 X1
Z1 Y1 X0
Z1 Y1 X1
None
INH 6
A 11
B 10
C 9
8
X0 12
X1 13
Y0
Y1
Z0
Z1
2
1
5
3
16
V
DD
LEVEL
CONVERTER
CMOS IC
BINARY TO 1 - OF - 2
DECODER WITH
INHIBIT
V
SS
7
V
EE
14 X
15 Y
4 Z
Figure 2. UTC 4053 Functional Diagram
"ON" RESISTANCE, R
ON
(OHMS)
350
T
a
=25℃
"ON" RESISTANCE, R
ON
(OHMS)
V
DD
= 7.5 V
V
EE
= - 7.5 V
300
250
200
150
100
50
0
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
350
V
DD
= 5.0 V
V
EE
= -5.0 V
300
T
a
=25℃
250
200
150
100
50
0
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
INPUT VOLTAGE, Vin (VOLTS)
INPUT VOLTAGE, Vin (VOLTS)
"ON" RESISTANCE, R
ON
(OHMS)
350
V
DD
= 2.5 V
300 V
EE
= - 2.5 V
T
a
=25℃
250
200
150
100
50
0
-10 -8.0 -6.0 -4.0 -2.0
0
2.0 4.0 6.0 8.0 10
INPUT VOLTAGE, Vin (VOLTS)
UTC
UNISONIC TECHNOLOGIES
CO., LTD.
5
QW-R502-036,A
www.unisonic.com.tw
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