®
ISL6115, ISL6116, ISL6117, ISL6120
Data Sheet
February 6, 2007
FN9100.4
Power Distribution Controllers
This family of fully featured hot swap power controllers
targets applications in the +2.5V to +12V range. The
ISL6115 is for +12V control, the ISL6116 for +5V, the
ISL6117 for +3.3V and the ISL6120 for +2.5V control
applications. Each has a hard wired undervoltage (UV)
monitoring and reporting threshold level approximately 80%
of the aforementioned voltage.
The ISL6115 has an integrated charge pump allowing
control of up to +16V rails using an external N-Channel
MOSFET whereas the other devices utilize the +12V bias
voltage to fully enhance the N-channel pass FET. All ICs
feature programmable overcurrent (OC) detection, current
regulation (CR) with time delay to latch-off and soft-start.
The current regulation level is set by 2 external resistors;
R
ISET
sets the CR Vth and the other is a low ohmic sense
element across, which the CR Vth is developed. The CR
duration is set by an external capacitor on the CTIM pin,
which is charged with a 20µA current once the CR Vth level
is reached. If the voltage on the CTIM cap reaches 1.9V the
IC then quickly pulls down the GATE output latching off the
pass FET.
This family although designed for high side switch control the
ISL6116, ISL6117, ISL6120 can also be used in a low side
configuration for control of much higher voltage potentials.
Features
• HOT SWAP Single Power Distribution Control (ISL6115
for +12V, ISL6116 for +5V, ISL6117 for +3.3V and ISL6120
for +2.5V)
• Overcurrent Fault Isolation
• Programmable Current Regulation Level
• Programmable Current Regulation Time to Latch-Off
• Rail to Rail Common Mode Input Voltage Range (ISL6115)
• Internal Charge Pump Allows the use of N-Channel
MOSFET for +12V control (ISL6115)
• Undervoltage and Overcurrent Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn On
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• 1µs Response Time to Dead Short
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Tape & Reel Packing with ‘-T’ Part Number Suffix
Applications
• Power Distribution Control
• Hot Plug Components and Circuitry
Ordering Information
PART
NUMBER
ISL6115CB*
ISL6116CB*
ISL6117CB*
ISL6120CB*
PART
MARKING
ISL61 15CB
ISL61 16CB
ISL61 17CB
ISL61 20CB
TEMP.
PKG.
RANGE (°C) PACKAGE DWG. #
0 to +85
0 to +85
0 to +85
0 to +85
0 to +85
0 to +85
0 to +85
0 to +85
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
(Pb-free)
8 Ld SOIC
(Pb-free)
8 Ld SOIC
(Pb-free)
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
M8.15
Pinout
ISL6115, ISL6116, ISL6117, ISL6120
(8 LD SOIC)
TOP VIEW
ISET
ISEN
GATE
VSS
1
2
3
4
8
7
6
5
PWRON
PGOOD
CTIM
VDD
ISL6115CBZA* 6115 CBZ
(Note)
ISL6116CBZA* 6116 CBZ
(Note)
ISL6117CBZA* 6117 CBZ
(Note)
ISL6120CBZA* 6120 CBZ
(Note)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6115, ISL6116, ISL6117, ISL6120
Application One - High Side Controller
+
LOAD
-
Application Two - Low Side Controller
+VBUS
LOAD
1
2
3
4
ISL6115
ISL6116
ISL6117
ISL6120
8
PWRON
7
6
OC
5
PGOOD
4
5
3
6
2
7
1
PWRON
8
ISL6116/7/20
+V supply to be controlled
+12V
12V REG
OC
2
February 6, 2007
ISL6115, ISL6116, ISL6117, ISL6120
Simplified Block Diagram
V
DD
+
-
+
I
SET
-
+
+
V
REF
-
I
SEN
ENABLE
12V
PGOOD
UV
8V
-
POR
QN
Q
R
R
S
PWRON
ISL611X
UV DISABLE
OC
+
-
20µA
CLIM
7.5K
+
-
+
1.86V
-
20µA
RISING
EDGE
PULSE
CTIM
GATE
10µA
FALLING
EDGE
DELAY
18V
ENABLE
-
+
WOCLIM
V
SS
18V
V
DD
Pin Descriptions
PIN #
1
2
3
SYMBOL
ISET
ISEN
GATE
FUNCTION
Current Set
Current Sense
External FET Gate Drive
Pin
Chip Return
Chip Supply
Current Limit Timing
Capacitor
Power Good Indicator
12V chip supply. This can be either connected directly to the +12V rail supplying the switched
load voltage or to a dedicated V
SS
+12V supply.
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The duration
of current limit time-out is equal to 93kΩ x C
TIM
.
Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain
N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV
level for the particular IC.
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven
high to a maximum of 5V or is left open. After a current limit time out, the chip is reset by a
low level signal applied to this pin. This input has 20μA pull up capability.
DESCRIPTION
Connect to the low side of the current sense resistor through the current limiting set resistor. This
pin functions as the current limit programming pin.
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor.
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground
sets the turn-on ramp. At turn-on this capacitor will be charged to V
DD
+5V (ISL6115) and to
V
DD
(ISL6116, ISL6117, ISL6120) by a 10μA current source.
4
5
6
VSS
V
DD
CTIM
7
PGOOD
8
PWRON
Power ON
3
February 6, 2007
ISL6115, ISL6116, ISL6117, ISL6120
Absolute Maximum Ratings
T
A
= +25°C
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+8V
ISEN, PGOOD, PWRON, CTIM, ISET. . . . . . . -0.3V to V
DD
+ 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5kV
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Operating Conditions
V
DD
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . +12V
±15%
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . . 0°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for
details.)
2. All voltages are relative to GND, unless otherwise specified
3. G.N.T. Guaranteed by design and characterization but Not Tested.
Electrical Specifications
PARAMETER
CURRENT CONTROL
ISET Current Source
ISET Current Source
Current Limit Amp Offset Voltage
Current Limit Amp Offset Voltage
GATE DRIVE
V
DD
= 12V, T
A
= T
J
= 0°C to +85°C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
I
ISET_ft
I
ISET_pt
Vio_ft
Vio_pt
T
J
= +15°C to +55°C
V
ISET
- V
ISEN
V
ISET
- V
ISEN,
T
J
= +15°C to +55°C
18.5
19
-6
-2
20
20
0
0
21.5
21
6
2
μA
μA
mV
mV
GATE Response Time To Severe OC
GATE Response Time to Overcurrent
GATE Turn-On Current
GATE Pull Down Current
GATE Pull Down Current
(3)
ISL6115 Undervoltage Threshold
ISL6115 GATE High Voltage
ISL6116 Undervoltage Threshold
ISL6117 Undervoltage Threshold
ISL6120 Undervoltage Threshold
ISL6116, 17, 20 GATE High Voltage
BIAS
V
DD
Supply Current
V
DD
POR Rising Threshold
V
DD
POR Falling Threshold
V
DD
POR Threshold Hysteresis
PWRON Pull-Up Voltage
PWRON Rising Threshold
PWRON Hysteresis
PWRON Pull-Up Current
pd_woc_amp
pd_oc_amp
I
GATE
OC_GATE_I_4V
WOC_GATE_I_4V
12V
UV_VTH
12VG
5V
UV_VTH
3V
UV_VTH
2V
UV_VTH
VG
V
GATE
to 10.8V
V
GATE
to 10.8V
V
GATE
to = 6V
Overcurrent
Severe Overcurrent
-
-
8.4
45
0.5
9.2
100
600
10
75
0.8
9.6
V
DD
+ 5V
4.35
2.6
1.85
V
DD
-
-
11.6
-
-
10
-
4.5
2.8
1.9
-
ns
ns
μA
mA
A
V
V
V
V
V
V
GATE Voltage
V
DD
+ 4.5V
4.0
2.4
1.8
GATE Voltage
V
DD
- 1.5V
I
VDD
V
DD_POR_L2H
V
DD_POR_H2L
V
DD_POR_HYS
PWRN_V
PWR_Vth
PWR_hys
PWRN_I
VDD Low to High
VDD High to Low
V
DD_POR_L2H -
V
DD_POR_H2L
PWRON Pin Open
-
7.8
7.5
0.1
2.7
1.4
130
9
3
8.4
8.1
0.3
3.2
1.7
170
17
5
9
8.7
0.6
-
2.0
250
25
mA
V
V
V
V
V
mV
μA
4
February 6, 2007
ISL6115, ISL6116, ISL6117, ISL6120
Electrical Specifications
PARAMETER
V
DD
= 12V, T
A
= T
J
= 0°C to +85°C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
(Continued)
MIN
TYP
MAX UNITS
CURRENT REGULATION DURATION/POWER GOOD
C
TIM
Charging Current
C
TIM
Fault Pull-Up Current (Note 3)
Current Limit Time-Out Threshold Voltage
Power Good Pull Down Current
C
TIM
_Vth
PG_Ipd
CTIM Voltage
V
OUT
= 0.5V
C
TIM
_ichg0
V
CTIM
= 0V
16
-
1.3
-
20
20
1.8
8
23
-
2.3
-
μA
mA
V
mA
Description and Operation
The members of this family are single power supply
distribution controllers for generic hot swap applications
across the +2.5V to +12V supply range. The ISL6115 is
targeted for +12V switching applications whereas the
ISL6116 is targeted for +5V, the ISL6117 for +3.3V and the
ISL6120 for +2.5V applications. Each IC has a hardwired
undervoltage (UV) threshold level approximately 17% lower
than the stated voltages.
These ICs feature a highly accurate programmable
overcurrent (OC) detecting comparator, programmable
current regulation (CR) with programmable time delay to latch
off, and programmable soft-start turn-on ramp all set with a
minimum of external passive components. The ICs also
include severe OC protection that immediately shuts down the
MOSFET switch should a rapid load current transient such as
a near dead short cause the CR Vth to exceed the
programmed level by 150mV. Additionally, the ICs have a UV
indicator and an OC latch indicator. The functionality of the
PGOOD feature is enabled once the IC is biased, monitoring
and reporting any UV condition on the ISEN pin.
Upon initial power up, the IC can either isolate the voltage
supply from the load by holding the external N-Channel
MOSFET switch off or apply the supply rail voltage directly to
the load for true hot swap capability. The PWRON pin must
be pulled low for the device to isolate the power supply from
the load by holding the external N-channel MOSFET off.
With the PWRON pin held high or floating the IC will be in
true hot swap mode. In both cases the IC turns on in a soft-
start mode protecting the supply rail from sudden in-rush
current.
At turn-on, the external gate capacitor of the N-Channel
MOSFET is charged with a 10μA current source resulting in
a programmable ramp (soft-start turn-on). The internal
ISL6115 charge pump supplies the gate drive for the 12V
supply switch driving that gate to ~V
DD
+5V, for the other
three ICs the gate drive voltage is limited to the chip bias
voltage, VDD.
Load current passes through the external current sense
resistor. When the voltage across the sense resistor exceeds
the user programmed CR voltage threshold value, (see
Table 1 for R
ISET
programming resistor value and resulting
nominal current regulation threshold voltage, V
CR
) the
controller enters its current regulation mode. At this time, the
time-out capacitor, on C
TIM
pin is charged with a 20μA current
source and the controller enters the current limit time to latch-
off period. The length of the current limit time to latch-off
duration is set by the value of a single external capacitor (see
Table 2) for CTIM capacitor value and resulting nominal
current limited time out to latch-off duration placed from the
CTIM pin (pin 6) to ground. The programmed current level is
held until either the OC event passes or the time out period
expires. If the former is the case then the N-Channel
MOSFET is fully enhanced and the C
TIM
capacitor is
discharged. Once CTIM charges to 1.87V, signaling that the
time out period has expired an internal latch is set whereby
the FET gate is quickly pulled to 0V turning off the N-Channel
MOSFET switch, isolating the faulty load.
TABLE 1.
R
ISET
RESISTOR
10kΩ
4.99kΩ
2.5kΩ
750Ω
NOTE: Nominal Vth = R
ISET
x 20μA.
TABLE 2.
C
TIM
CAPACITOR
0.022μF
0.047μF
0.1μF
NOMINAL CURRENT LIMITED PERIOD
2ms
4.4ms
9.3ms
NOMINAL OC VTH
200mV
100mV
50mV
15mV
NOTE: Nominal time-out period = C
TIM
x 93kΩ.
This IC responds to a severe overcurrent load (defined as a
voltage across the sense resistor >150mV over the OC Vth set
point) by immediately driving the N-Channel MOSFET gate to
0V in about 10μs. The gate voltage is then slowly ramped up
turning on the N-Channel MOSFET to the programmed current
regulation level; this is the start of the time out period.
Upon a UV condition the PGOOD signal will pull low when
tied high through a resistor to the logic or VDD supply. This
pin is a UV fault indicator. For an OC latch off indication,
monitor CTIM, pin 6. This pin will rise rapidly from 1.9V to
VDD once the time out period expires.
See Figures 12 to 16 for waveforms relevant to text.
The IC is reset after an OC latch-off condition by a low level
on the PWRON pin and is turned on by the PWRON pin
being driven high.
5
February 6, 2007
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