DATASHEET
ISL6412
Triple Output, Low-Noise LDO Regulator with Integrated Reset Circuit
The ISL6412 is an ultra low noise triple output LDO regulator
with microprocessor reset circuit and is optimized for
powering wireless chip sets. The IC accepts an input voltage
range of 3.0V to 3.6V and provides three regulated output
voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-clean
2.8V (LDO3). On chip logic provides sequencing between
LDO1 and LDO2 for the BBP/MAC and the I/O supply
voltage outputs. LDO3 features ultra low noise that does not
typically exceed 30µV RMS to aid VCO stability. High
integration and the thin Quad Flat No-lead (QFN) package
makes the ISL6412 an ideal choice to power many of today’s
small form factor industry standard wireless cards such as
PCMCIA, mini-PCI and Cardbus-32.
The ISL6412 uses an internal PMOS transistor as the pass
device. The ISL6412 also integrates a reset function, which
eliminates the need for the additional reset IC required in
WLAN applications. The IC asserts a RESET signal
whenever the VIN supply voltage drops below a preset
threshold, keeping it asserted for a time set by a capacitor to
GND after VIN has risen above the reset threshold. FAULT1
indicates the loss of regulation on LDO1.
FN9067
Rev 1.00
Mar 20, 2007
Features
• Small DC/DC Converter Size
- Three LDOs and Reset Circuitry in a Low-Profile
4x4mm QFN Package
• High Output Current
- LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA
- LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA
- LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
• Ultra-Low Dropout Voltage
- LDO2, 2.8V. . . . . . . . . . . . . . . . 125mV (typ.) at 225mA
- LDO3, 2.8V. . . . . . . . . . . . . . . . 100mV (typ.) at 125mA
• Ultra-Low Output Voltage Noise
- <30V
RMS
(typ.) for LDO3 (VCO Supply)
• Stable with Small Ceramic Output Capacitors
• Extensive Protection and Monitoring Features
- Over current protection
- Short circuit protection
- Thermal shutdown
- FAULT indicator
• Logic-Controlled Shutdown Pin
Ordering Information
PART
NUMBER
ISL6412IR
ISL6412IR-TK
PART
MARKING
ISL6412IR
ISL6412IR
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
• Integrated Microprocessor Reset Circuit
- Programmable Reset Delay
• Proven Reference Design for a Total WLAN System
Solution
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint Improves PCB
Efficiency and Is Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
-40 to +85 16 Ld 4x4 QFN L16.4x4
-40 to +85 16 Ld 4x4 QFN L16.4x4
-40 to +85 16 Ld 4x4 QFN L16.4x4
-40 to +85 16 Ld 4x4 QFN L16.4x4
(Pb-free)
-40 to +85 16 Ld 4x4 QFN L16.4x4
(Pb-free)
ISL6412IR-T5K ISL6412IR
ISL6412IRZ
(Note 2)
6412IRZ
ISL6412IRZ-TK 6412IRZ
(Notes 1, 2)
NOTES:
1. Tape and Reel available. Add “-T” suffix for Tape and Reel Packing
Option
2. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Applications
• PRISM® 3 Chipsets – ISL37106P
• WLAN Cards
- PCMCIA, Cardbus32, MiniPCI Cards
- Compact Flash Cards
• Liberty Chipset
• Hand-Held Instruments
FN9067 Rev 1.00
Mar 20, 2007
Page 1 of 11
ISL6412
Absolute Maximum Ratings
V
IN
, SHDN to GND/GND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
SET, CC, FAULT to GND/GND3 . . . . . . . . . . . . . . . . . -0.3V to 7.0V
Output Current (Continuous)
LDO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA
LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA
LDO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
QFN Package (Notes 3, 4) . . . . . . . .
46
9
Maximum Junction Temperature (Plastic Package) -55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
GENERAL SPECIFICATIONS
V
IN
Voltage Range
Operating Supply Current
Shutdown Supply Current
SHDN Input Threshold
V
IN
= +3.3V, Compensation Capacitor = 33nF, T
A
= +25°C, unless otherwise noted.
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.0
I
OUT
= 0mA
SHDN = GND
V
IH
, V
IN
= 3V to 3.6V
V
IL
, V
IN
= 3V to 3.6V
-
-
2.0
-
145
-
C
OUT
= 10F, V
OUT
= 90% of final
value
Rising 75mV Hysteresis
-
2.4
3.3
830
5
-
-
150
20
120
2.45
3.6
1125
10
-
0.4
160
-
-
2.6
V
A
A
V
V
°C
°C
s
V
Thermal Shutdown Temperature (Note 7)
Thermal Shutdown Hysteresis (Note 7)
Start-up Time (Note 7)
Input Undervoltage Lockout
LDO1 SPECIFICATIONS
Output Voltage (V
OUT1
)
Output Voltage Initial Accuracy
Line Regulation
Load Regulation
Maximum Output Current (I
OUT1
) (Note 7)
Output Current Limit (Note 7)
Output Voltage Noise (Note 7)
LDO2 SPECIFICATIONS
Output Voltage (V
OUT2
)
Output Voltage Accuracy
Maximum Output Current (I
OUT2
) (Note 7)
Output Current Limit (Note 7)
Dropout Voltage (Notes 5, 7)
Line Regulation
Load Regulation
I
OUT
= 225mA
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
I
OUT
= 10mA to 225mA
I
OUT
= 10mA, T
A
= -40°C to 85°C
V
IN
= 3.6V
10Hz < f < 100kHz, C
OUT
= 4.7F,
I
OUT
= 50mA
I
OUT
= 10mA, T
A
= -40°C to 85°C
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
I
OUT
= 10mA to 330mA
-
-2.0
-0.15
-1.5
330
500
-
1.8
-
0.0
-
-
600
115
-
2.0
0.15
1.5
-
1105
-
V
%
%/V
%
mA
mA
V
RMS
-
-2.0
225
330
-
-0.15
-
2.8
-
-
-
125
0.0
0.2
-
2.0
-
900
160
0.15
1.0
V
%
mA
mA
mV
%/V
%
FN9067 Rev 1.00
Mar 20, 2007
Page 4 of 11
ISL6412
Electrical Specifications
PARAMETER
Output Voltage Noise (Note 7)
V
IN
= +3.3V, Compensation Capacitor = 33nF, T
A
= +25°C, unless otherwise noted.
(Continued)
TEST CONDITIONS
10Hz < f < 100kHz, I
OUT
= 10mA
C
OUT
= 2.2F
C
OUT
= 10F
LDO3 SPECIFICATIONS
Output Voltage (V
OUT3
)
Output Voltage Accuracy
Maximum Output Current (I
OUT3
) (Note 7)
Output Current Limit (Note 7)
Dropout Voltage (Notes 5, 7)
Line Regulation
Load Regulation
Output Voltage Noise (Note 7)
I
OUT
= 125mA
V
IN
= 3.0V to 3.6V, I
OUT
= 10mA
I
OUT
= 10mA to 125mA
10Hz < f < 100kHz, I
OUT
= 10mA
C
OUT
= 2.2F
C
OUT
= 10F
RESET BLOCK SPECIFICATIONS
Reset Threshold
Reset Threshold Hysteresis (Note 7)
V
IN
to Reset Delay
RESET Active Timeout Period (Notes 6, 7)
FAULT1
Rising Threshold
Falling Threshold
NOTES:
5. The dropout voltage is defined as V
IN
- V
OUT
, when V
OUT
is 50mV below the value of V
OUT
for V
IN
= V
OUT
+ 0.5V.
6. The RESET time is linear with CT at a slope of ~5ms/nF. Thus, at 10nF (0.01F) the RESET time is 50ms.
7. Guaranteed by design, not production tested.
% of V
OUT
% of V
OUT
+5.5
-10.5
+8.0
-8.0
+10.5
-5.5
%
%
VCC = V
TH
to V
TH
- 100mV
CT = 0.01µF
2.564
6.3
-
50
2.630
-
20
-
2.66
-
-
-
V
mV
s
ms
-
-
30
20
-
-
V
RMS
V
RMS
I
OUT
= 10mA, T
A
= -40°C to +85°C
V
IN
= 3.6V
-
-2.0
225
300
-
-0.15
-
2.8
-
-
450
100
0.0
0.2
-
2.0
-
840
160
0.15
1.0
V
%
mA
mA
mV
%/V
%
-
-
65
60
-
-
V
RMS
V
RMS
MIN
TYP
MAX
UNITS
Typical Performance Curves
The test conditions for the Typical Operating Performance are: V
IN
= 3.3V, T
A
= +25°C,
Unless Otherwise Noted
SHDN
1V/DIV
VOUT2
1V/DIV
SHDN
1V/DIV
VOUT3
1V/DIV
VOUT2
1V/DIV
VOUT3
1V/DIV
VOUT1
1V/DIV
VOUT1
1V/DIV
100µs/DIV
100µs/DIV
FIGURE 1. START-UP SEQUENCE
FIGURE 2. SHUTDOWN SEQUENCE
FN9067 Rev 1.00
Mar 20, 2007
Page 5 of 11
Embedded System
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