Field Programmable Gate Array, 190MHz, 144-Cell, CMOS, CPGA132
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | LSC/CSI |
| package instruction | PGA, PGA132,14X14 |
| Reach Compliance Code | unknown |
| Other features | MAX 96 I/OS FOR 3042 SERIES; 480 FLIP-FLOPS |
| maximum clock frequency | 152 MHz |
| Combined latency of CLB-Max | 4.1 ns |
| JESD-30 code | S-CPGA-P132 |
| JESD-609 code | e0 |
| Configurable number of logic blocks | 144 |
| Equivalent number of gates | 4200 |
| Number of entries | 110 |
| Number of logical units | 144 |
| Output times | 110 |
| Number of terminals | 132 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| organize | 144 CLBS, 4200 GATES |
| Package body material | CERAMIC, METAL-SEALED COFIRED |
| encapsulated code | PGA |
| Encapsulate equivalent code | PGA132,14X14 |
| Package shape | SQUARE |
| Package form | GRID ARRAY |
| power supply | 5 V |
| Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
| Certification status | Not Qualified |
| Maximum supply voltage | 5.25 V |
| Minimum supply voltage | 4.75 V |
| Nominal supply voltage | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | PIN/PEG |
| Terminal pitch | 2.54 mm |
| Terminal location | PERPENDICULAR |
| Base Number Matches | 1 |