CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
SYMBOL
BIAS
V
DD
I
DD
V
DD
_LO
V
DD
_LOR
VMON
V
REF
V
REFHYST
V
REF_RNG
t
FIL
RESET
I
PD
R
PU
V
OL
t
RPD
MANUAL RESET
V
MR
V
MRHYST
I
PU
t
MD
t
MR
NOTE:
V
DD
= 3.3V, T
A
= T
J
= -40°C to +85°C, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
Supply Voltage Range
V
DD
Supply Current
V
DD
Lock Out
V
DD
Lock Out Reset
VMON > V
REF
V
DD
low to high
V
DD
high to low
2.7
165
2.6
2.4
4.0
1000
V
µA
V
V
Adj. Reset Threshold Voltage
Hysteresis of V
REF
Range
Glitch Filter Duration
V
REF
(max) - V
REF
(min)
VMON glitch to RST low Filter
619
635
10
1.8
30
651
mV
mV
mV
µs
Pull-down Current
Internal Pull-up Resistance
Output Low
V
TH
to Reset Asserted Delay
RST = 0.5V
2
20
mA
k
0.1
V
µs
V
DD
= 1V
Last valid input = V
TH
to RST release
0.05
1.5
MR Input Voltage
Hysteresis of V
MR
Pull-up Current
MR to Deassert Reset Out Delay
MR to Assert Reset Out Delay
MR low to high threshold
0.4V
DD
0.5V
DD
0.065
0.6V
DD
V
V
µA
ns
ns
MR = 0.5V
MR high to RST release
MR low to RST pulling low
10
50
15
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN9229 Rev 2.00
April 29, 2010
Page 3 of 7
ISL88041
ISL88041 Description and Operation
The ISL88041 is a four voltage detection IC designed to
monitor multiple voltages
0.7V.
This IC is suitable for
microprocessors or industrial system applications providing
both reset and manual reset functions.
undervoltage threshold (V
TRIP
) by connecting individual
VMON pins to an external resistor divider according to the
Equation 1:
V
TRIP
=
0.635V
R1
+
R2
R2
(EQ. 1)
V
DD
Lock Out
Applying power to the ISL88041 V
DD
activates a lock out circuit
which disables the reporting function until V
DD
rises to ~2.6V.
As V
DD
bias is applied the RST output is held low before
V
DD
= 1V. If V
DD
falls below ~2.4V the lock out of monitoring
and reporting functions is invoked.
See Figure 8 for a typical application configuration.
Manual Reset
The manual-reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling the input low.
Reset is asserted and deasserted immediately upon MR
transitioning through MR
VTH
, see Figures 6 and 7.
Figure 1 is the operational timing diagram.
Low Voltage Monitoring
Once biased to 2.7V the IC continuously monitors and
reports from one to four voltages independently through
external resistor dividers comparing each VMON pin voltage
to a nominal internal 0.635V reference. Once all VMON input
voltages rise above this threshold, the RST output is
immediately deasserted by being released to be pulled high
via its internal 20k
(or optional external) pull resistor to V
DD
indicating that all the minimum voltage conditions have been
met (see Figure 4). The RST output is open-drain to allow
ORing of signals and interfacing to a range of logic levels.
Once any VMON input falls below its respective user-set
threshold, the RST output is pulled low after the glitch filter
delay (t
FIL
) as the VMON inputs are designed to reject short
undervoltage transients of approximately 30µs (see
Figure 5). The user can customize the individual rail
Using the ISL88041EVAL1
The ISL88041EVAL1 is the evaluation platform for this
product and illustrates the flexibility and simplicity of
monitoring four separate voltages. The RST output can be
monitored once the V
DD
, GND, and appropriate 3.3V, 2.5V,
1.8V and 1.2V supply voltage inputs are properly biased as
labeled. A Manual Reset (MR) input is also available for
evaluation.
The circuit as shown in Figures 10 and 11 has resistor
dividers chosen to monitor for an undervoltage threshold
level of 89% of the 4 nominal voltages. Figure 1 illustrates
the expected behavior and Figures 4 through 7 illustrate the
actual IC performance in the ISL88041EVAL1.
V
TH
VMON
1V
<t
FIL
t
MR
MR
t
RPD
>t
FIL
t
MD
RST
FIGURE 1. ISL88041 OPERATIONAL TIMING DIAGRAM
FN9229 Rev 2.00
April 29, 2010
Page 4 of 7
ISL88041
Typical Performance Curves
0.6
0.5
V
DD
BIAS CURRENT (mA)
VMON < VMON
_L2H
VMON THRESHOLD (V)
VMON > VMON
_L2H
0.645
0.642
0.639
0.636
0.633
0.630
0.627
2.6
3.0
3.33
3.66
4.0
V
DD
BIAS VOLTAGE (V)
Figure 2 illustrates the idle and active bias currents levels.
0.4
0.3
0.2
0.1
0
2.6
3.3
3.5
3.7
3.9
V
DD
BIAS VOLTAGE (V)
Figure 3 shows the VMON threshold shift over the bias range,
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