- Differential input voltage range equal to the power
supply voltage
- Low output saturation voltage: 250 mV at 4 mA
- Output voltage compatible with TTL, DTL, ECL,
MOS and CMOS logic systems
- 8-pin PDIP and SOP
Pb-Free
packages
General Description
The AP393 consists of two independent precision
voltage comparators with an offset voltage
specification as low as 2.0 mV max for two
comparators which were designed specifically to
operate from a single power supply over a wide
range of voltages. Operation from split power
supplies is also possible and the low power supply
current drain is independent of the magnitude of the
power supply voltage. These comparators also
have a unique characteristic in that the input
common-mode voltage range includes ground,
even though operated from a single power supply
voltage.
Application areas include limit comparators, simple
analog to digital converters; pulse, squarewave and
time delay generators; wide range VCO; MOS clock
timers; multivibrators and high voltage digital logic
gates. The AP393 is designed to directly interface
with TTL and CMOS. When operated from both
plus and minus power supplies, the AP393 will
directly interface with MOS logic where their low
power drain is a distinct advantage over standard
comparators.
Advantages
- High precision comparators
- Reduced V
OS
drift over temperature
- Eliminates need for dual supplies
- Allows sensing near ground
- Compatible with all forms of logic
- Power drain suitable for battery operation
Pin Assignment
(Top View)
OUTPUT 1 1
INVERTING INPUT 1 2
NON-INVERTING INPUT 1 3
GND 4
8
AP393
7
6
5
V
+
OUTPUT 2
INVERTING INPUT 2
NON-INVERTING INPUT 2
SOP-8L/PDIP-8L
Pin Descriptions
Pin Name
OUTPUT 1
INVERTING
INPUT 1
NON-INVERT
ING INPUT 1
GND
Pin
No.
1
2
3
4
Description
Channel 1 Output
Channel 1 Negative Input
Channel 1 Positive Input
Ground
Pin Name
NON-INVERT
ING INPUT 2
INVERTING
INPUT 2
OUTPUT 2
+
V
Pin
No.
5
6
7
8
Description
Channel 2 Positive Input
Channel 2 Negative Input
Channel 2 Output
Vcc
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.0 Sep 7, 2004
1/13
AP393
Low Power Low Offset Voltage Dual Comparators
Ordering Information
AP393 X X
Package
N: PDIP-8L
S: SOP-8L
Packing
Blank: Tube
A : Taping
Block Diagram
OUTPUT 1
1
8
V+
INVERTING INPUT 1
2
A
B
+ +
-
7
OUTPUT 2
NON-INVERTING INPUT 1 3
-
6
INVERTING INPUT 2
GND
4
5
NON-INVERTING INPUT 2
V
+
3.5µA
100µA
3.5µA
100µA
Q2
+INPUT
Q1
Q3
Q4
Q5
OUTPUT
-INPUT
Q6
Q8
Q7
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.0 Sep 7, 2004
2/13
AP393
Low Power Low Offset Voltage Dual Comparators
Absolute Maximum Ratings
(Note 10)
Symbol
V
CC
V
IN
V
IN
I
CC
P
D
T
OP
T
ST
T
Lead
Parameter
Supply Voltage
Differential Input Voltage
(Note 8)
Input Voltage
Input Current (V
IN
-0.3V)
(Note 3)
Molded DIP
Power Dissipation
(Note 1)
Metal Can
Small Outline Package
Output Short-Circuit to Ground
(Note 2)
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering, 10 sec)
PDIP Soldering (10 sec)
Soldering Information
Vapor Phase (60 sec)
SOP
Infrared (15 sec)
ESD rating (1.5kΩ in with 100pF)
Rating
36
36
-0.3 to +36
50
780
660
510
Continuous
0 to +70
-65 to +150
+260
+260
+215
+220
1300
Unit
V
V
V
mA
mW
o
o
C
C
o
C
o
C
V
Electrical Characteristics
(V
CC
=5V, T
A
=25
o
C, unless otherwise stated)
Symbol
Parameter
V
OFFSET
Input Offset Voltage
I
BIAS
I
OFFSET
I
CC
Input Bias Current
Conditions
(Note 9)
Min.
-
-
-
0
-
-
50
-
-
6.0
-
-
Typ.
1.0
25
5.0
-
0.4
1
200
300
1.3
16
250
0.1
Max.
5.0
250
50
V -1.5
1
2.5
+
Unit
mV
nA
nA
V
mA
V/mV
ns
µs
mA
mV
nA
I
O(Sink)
V
SAT
I
O(Leak)
I
IN
(+) or I
IN
(-) with Output In
Linear Range, V
CM
=0V
(Note 5)
Input Offset Current
I
IN
(+) - I
IN
(-) V
CM
=0V
Input Common Mode Voltage Range V
+
=30V
(Note 6)
V
+
=5V
Supply Current
R
L
=∞
V
+
=36V
+
R
L
> 15kΩ, V =15V
Voltage Gain
V
O
=1V to 11V
V
IN
=TTL Logic Swing,
Large Signal Response Time
V
REF
=1.4V, V
RL
=5V, R
L
=5.1kΩ
Response Time
V
RL
=5V, R
L
=5.1kΩ
(Note 7)
Output Sink Current
V
IN
(-)=1V, V
IN
(+)=0, V
O
<1.5V
V
IN
(-)=1V, V
IN
(+)=0, I
SINK
<
Saturation Voltage
4mA
Output Leakage Current
V
IN
(-)=0, V
IN
(+)=1V, V
O
=5V
-
-
-
-
400
-
Electrical Characteristics
(V
CC
=5V)
(Note 4)
Symbol
Parameter
V
OFFSET
Input Offset Voltage
I
OFFSET
Input Offset Current
I
BIAS
V
SAT
I
O(Leak)
Conditions
(Note 9)
I
IN
(+) -I
IN
(-), V
CM
=0V
I
IN
(+) or I
IN
(-) with Output In
Input Bias Current
Linear Range, V
CM
=0V
(Note 5)
Input Common Mode Voltage Range V
+
=30V
(Note 6)
V
IN
(-)=1V, V
IN
(+)=0, I
SINK
<
Saturation Voltage
4mA
Output Leakage Current
V
IN
(-)=0, V
IN
(+)=1V, V
O
=30V
Keep All V
IN
’s > 0V (or V
-
, if
Differential Input Voltage
Used),
(Note 8)
Min.
-
-
-
0
-
-
-
Typ.
-
-
-
-
-
-
-
Max.
9
150
400
V
+
-2.0
700
1.0
36
Unit
mV
nA
nA
V
mV
µA
V
Anachip Corp.
www.anachip.com.tw
3/13
Rev. 1.0 Sep 7, 2004
AP393
Low Power Low Offset Voltage Dual Comparators
Note 1:
For operating at high temperatures, the AP393 must be derated based on a 125°C maximum junction temperature and a
thermal resistance of 170°C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient.
The AP393 must be derated based on a 150°C maximum junction temperature. The low bias dissipation and the “ON-OFF”
characteristic of the outputs keeps the chip dissipation very small (P
D
<100 mW), provided the output transistors are allowed
to saturate.
+
Note 2:
Short circuits from the output to V can cause excessive heating and eventual destruction. When considering short circuits to
+
ground, the maximum output current is approximately 20 mA independent of the magnitude of V .
Note 3:
This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base
junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this
diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output
+
voltages of the comparators to go to the V voltage level (or to ground for a large overdrive) for the time duration that an input
is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which is negative,
again returns to a value greater than -0.3V.
Note 4:
The AP393 temperature specifications are limited to 0°C < T
A
< +70°C.
Note 5:
The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent
of the state of the output so no loading change exists on the reference or input lines.
Note 6:
The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The
+
upper end of the common-mode voltage range is V -1.5V at 25°C, but either or both inputs can go to 36V without damage,
+
independent of the magnitude of V .
Note 7:
The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 300 ns can be
obtained, see typical performance characteristics section.
Note 8:
Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the
common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than
-0.3V (or 0.3V below the magnitude of the negative power supply, if used).
+
+
Note 9:
At output switch point, V
O
~ 1.4V, R
S
=0Ω with V from 5V to 30V; and over the full input common-mode range (0V to V -1.5V),
at 25°C.
Note 10:
Refer to RETS193AX for AP393 military specifications.
京公网安备 11010802033920号
EEWORLD
