531FB945M000DGR datasheet, PDF

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531FB945M000DGR: DescriptionLVDS Output Clock Oscillator, 10MHz Min, 945MHz Max, 945MHz Nom, ROHS COMPLIANT PACKAGE-6; CategoryPassive components oscillator; File Size2MB，26 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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531FB945M000DGR Overview

LVDS Output Clock Oscillator, 10MHz Min, 945MHz Max, 945MHz Nom, ROHS COMPLIANT PACKAGE-6

531FB945M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT PACKAGE-6
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	SI531
Installation features	SURFACE MOUNT
Number of terminals	6
Maximum operating frequency	945 MHz
Minimum operating frequency	10 MHz
Nominal operating frequency	945 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
Package body material	PLASTIC/EPOXY
Encapsulate equivalent code	DILCC6,.2
physical size	7.0mm x 5.0mm x 1.85mm
power supply	2.5 V
Certification status	Not Qualified
longest rise time	0.35 ns
Maximum slew rate	98 mA
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

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S i531 6

RECISION

LOCK

ITTER

TTENUATOR

Features



Fixed frequency jitter attenuator

with selectable clock ranges at

19, 38, 77, 155, 311, and

622 MHz (710 MHz max)

Support for SONET, 10GbE,

10GFC, and corresponding FEC

rates

Ultra-low jitter clock output with

jitter generation as low as

0.3 ps

RMS

(50 kHz–80 MHz)

Integrated loop filter with

selectable loop bandwidth

(100 Hz–7.9 kHz)

Meets OC-192 GR-253-CORE

jitter specifications



Dual clock inputs with integrated

clock select mux

One clock input can be 1x, 4x, or

32x the frequency of the second

clock input

Single clock output with

selectable signal format:

LVPECL, LVDS, CML, CMOS

LOL, LOS alarm outputs

Pin programmable settings

On-chip voltage regulator for 1.8

±5%, 2.5 ±10%, or 3.3 V ±10%

operation

Small size (6 x 6 mm 36-lead

QFN)

Pb-free, RoHS compliant

Ordering Information:

See page 20.

Pin Assignments

Si5316

Applications



Optical modules

SONET/SDH OC-48/OC-192/

STM-16/STM-64 line cards

10GbE, 10GFC line cards



ITU G.709 line cards

Wireless basestations

Test and measurement

Synchronous Ethernet

Description

The Si5316 is a low jitter, precision jitter attenuator for high-speed

communication systems, including OC-48, OC-192, 10G Ethernet, and

10G Fibre Channel. The Si5316 accepts dual clock inputs in the 19, 38,

77, 155, 311, or 622 MHz frequency range and generates a jitter-

attenuated clock output at the same frequency. Within each of these clock

ranges, the device can be tuned approximately 15% higher than nominal

SONET/SDH frequencies, up to a maximum of 710 MHz in the 622 MHz

range. The Si5316 is based on Silicon Laboratories' 3rd-generation

DSPLL

technology, which provides any-frequency synthesis and jitter

attenuation in a highly integrated PLL solution that eliminates the need for

external VCXO and loop filter components. The DSPLL loop bandwidth is

digitally programmable, providing jitter performance optimization at the

application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the

Si5316 is ideal for providing jitter attenuation in high performance timing

applications.

Patents pending

Rev. 1.0 7/12

Si5316

Si5316

A B L E O F

O N T E N T S

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Phase Noise Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3. Typical Applications Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5. Pin Descriptions: Si5316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

7. Package Outline: 36-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

9.1. Si5316 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Rev. 1.0

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