MM74HC373 3-STATE Octal D-Type Latch
September 1983
Revised May 2005
MM74HC373
3-STATE Octal D-Type Latch
General Description
The MM74HC373 high speed octal D-type latches utilize
advanced silicon-gate CMOS technology. They possess
the high noise immunity and low power consumption of
standard CMOS integrated circuits, as well as the ability to
drive 15 LS-TTL loads. Due to the large output drive capa-
bility and the 3-STATE feature, these devices are ideally
suited for interfacing with bus lines in a bus organized sys-
tem.
When the LATCH ENABLE input is HIGH, the Q outputs
will follow the D inputs. When the LATCH ENABLE goes
LOW, data at the D inputs will be retained at the outputs
until LATCH ENABLE returns HIGH again. When a high
logic level is applied to the OUTPUT CONTROL input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 18 ns
s
Wide operating voltage range: 2 to 6 volts
s
Low input current: 1
P
A maximum
s
Low quiescent current: 80
P
A maximum (74 Series)
s
Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number
MM74HC373WM
MM74HC373SJ
MM74HC373MTC
MM74HC373N
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Output
Control
L
L
L
H
Latch
Enable
H
H
L
X
H
L
X
X
Data
373
Output
H
L
Q
0
Z
H HIGH Level
L LOW Level
Q
0
Level of output before steady-state input conditions were established.
Z High Impedance
Top View
© 2005 Fairchild Semiconductor Corporation
DS005335
www.fairchildsemi.com
MM74HC373
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
q
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
,V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
V
CC
V
CC
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
0
V
CC
V
2
Max
6
Units
V
0.5 to
7.0V
1.5 to V
CC
1.5V
0.5 to V
CC
0.5V
r
20 mA
r
35 mA
r
70 mA
65
q
C to
150
q
C
40
85
q
C
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
V
IH
or V
IL
2.0V
4.5V
6.0V
V
IN
V
IH
or V
IL
4.5V
6.0V
2.0V
4.5V
6.0V
V
IN
V
IH
or V
IL
4.5V
6.0V
6.0V
V
IH
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
|I
OUT
|
d
6.0 mA
|I
OUT
|
d
7.8 mA
I
IN
I
OZ
Maximum Input
Current
Maximum 3-STATE
Output Leakage
Current
I
CC
Maximum Quiescent
Supply Current
V
IN
I
OUT
V
CC
or GND
0
P
A
6.0V
8.0
80
160
V
IN
V
OUT
V
IH
or V
IL
, OC
V
CC
or GND
V
IN
V
CC
or GND
4.2
5.7
0
0
0
3.98
5.48
0.1
0.1
0.1
3.84
5.34
0.1
0.1
0.1
3.7
5.2
0.1
0.1
0.1
V
V
V
V
V
|I
OUT
|
d
6.0 mA
|I
OUT
|
d
7.8 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
V
IH
or V
IL
|I
OUT
|
d
20
P
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
Conditions
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
|I
OUT
|
d
20
P
A
T
A
Typ
1.5
3.15
4.2
0.5
1.35
1.8
25
q
C
T
A
40 to 85
q
C T
A
55 to 125
q
C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.5
3.15
4.2
0.5
1.35
1.8
Units
V
V
V
V
V
V
r
0.1
r
0.5
r
1.0
r
5
r
1.0
r
10
P
A
P
A
P
A
Note 4:
For a power supply of 5V
r
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
MM74HC373
AC Electrical Characteristics
V
CC
5V, T
A
25
q
C, t
r
t
f
6 ns
Parameter
Conditions
45 pF
45 pF
1 k
:
45 pF
1 k
:
5 pF
5
10
9
16
ns
ns
ns
18
25
ns
Typ
18
21
20
Guaranteed
Limit
25
30
28
Units
ns
ns
ns
Symbol
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
S
t
H
t
W
Maximum Propagation Delay, Data to Q C
L
Maximum Propagation Delay, LE to Q
Maximum Output Enable Time
Maximum Output Disable Time
Minimum Set Up Time
Minimum Hold Time
Minimum Pulse Width
C
L
R
L
C
L
R
L
C
L
AC Electrical Characteristics
V
CC
2.0
6.0V, C
L
50 pF, t
r
t
f
6 ns (unless otherwise specified)
Conditions
C
L
C
L
C
L
C
L
C
L
C
L
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
:
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
:
50 pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
50
80
21
30
19
26
50
21
19
150
200
30
40
26
35
150
30
26
50
9
9
5
5
5
30
10
9
25
7
6
30
50
5
10
10
10
80
16
14
60
12
10
188
250
37
50
31
44
188
37
31
60
13
11
5
5
5
100
20
18
75
15
13
225
300
45
60
39
53
225
45
39
75
15
13
5
5
5
120
24
20
90
18
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
V
CC
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
T
A
Typ
50
80
22
30
19
26
63
110
25
35
21
28
150
200
30
40
26
35
175
225
35
45
30
39
25
q
C
T
A
Symbol
Parameter
40 to 85
q
C T
A
55 to 125
q
C
Guaranteed Limits
188
250
37
50
31
44
220
280
44
56
37
49
225
300
45
60
39
53
263
338
52
68
45
59
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay, Data to Q
t
PHL
, t
PLH
Maximum Propagation
Delay, LE to Q
C
L
C
L
C
L
C
L
C
L
C
L
t
PZH
, t
PZL
Maximum Output
Enable Time
R
L
C
L
C
L
C
L
C
L
C
L
C
L
t
PHZ
, t
PLZ
Maximum Output Disable
Disable Time
t
S
Minimum Set Up Time
R
L
C
L
t
H
Minimum Hold Time
2.0V
4.5V
6.0V
t
W
Minimum Pulse Width
2.0V
4.5V
6.0V
t
THL
, t
TLH
Maximum Output Rise
and Fall Time
C
PD
Power Dissipation
Capacitance (Note 5)
C
IN
Maximum Input Capacitance
C
L
50 pF
2.0V
4.5V
6.0V
(per latch)
OC
OC
V
CC
GND
3
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