MM74HCT540 • MM74HCT541 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
February 1984
Revised May 2005
MM74HCT540 • MM74HCT541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HCT540 and MM74HCT541 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed operation even when driving large bus
capacitances. These circuits achieve speeds comparable
to low power Schottky devices, while retaining the low
power consumption of CMOS. Both devices are TTL input
compatible and have a fanout of 15 LS-TTL equivalent
inputs.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
The MM74HCT540 is an inverting buffer and the
MM74HCT541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
In order to enhance PC board layout, the MM74HCT540
and MM74HCT541 offers a pinout having inputs and out-
puts on opposite sides of the package. All inputs are pro-
tected from damage due to static discharge by diodes to
V
CC
and ground.
Features
s
TTL input compatible
s
Typical propagation delay: 12 ns
s
3-STATE outputs for connection to system buses
s
Low quiescent current: 80
P
A
s
Output current: 6 mA (min.)
Ordering Code:
Order Number
MM74HCT540WM
MM74HCT540SJ
MM74HCT540MTC
MM74HCT540N
MM74HCT541WM
MM74HCT541SJ
MM74HCT541MTC
MM74HCT541N
Package
Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT540
Top View
MM74HCT541
© 2005 Fairchild Semiconductor Corporation
DS006040
www.fairchildsemi.com
MM74HCT540 • MM74HCT541
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
)
500
ns
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
0.5 to
7.0V
1.5 to V
CC
1.5V
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
0.5 to V
CC
0.5V
Clamp Diode Current (I
IK
, I
OK
)
r
20 mA
r
35 mA
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
r
70 mA
Storage Temperature Range (T
STG
)
65
q
C to
150
q
C
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
600 mW
500 mW
260
q
C
Max
5.5
V
CC
Units
V
V
4.5
0
40
85
q
C
Lead Temperature (T
L
)
(Soldering 10 seconds)
DC Electrical Characteristics
V
CC
5V
r
10% (unless otherwise specified)
Parameter
Minimum HIGH Level
Input Voltage
V
IL
V
OH
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
V
OL
Maximum LOW Level
Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
I
IN
I
OZ
Maximum Input
Current
Maximum 3-STATE
Output Leakage
Current
I
CC
Maximum Quiescent
Supply Current
V
IN
I
OUT
V
IN
V
CC
or GND
0
P
A
2.4V or 0.5V (Note 4)
0.6
1.0
1.3
1.5
mA
8.0
80
160
V
OUT
G
V
IH
V
CC
or GND
V
IN
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
CC
or GND
4.5V
5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
4.5V
5.5V
V
CC
4.2
5.2
V
CC
0.1
3.98
4.98
V
CC
0.1
3.84
4.84
V
CC
0.1
3.7
4.7
V
V
V
0.8
0.8
0.8
V
Conditions
T
A
Typ
2.0
25
q
C
T
A
Symbol
V
IH
40 to 85
q
C T
A
55 to 125
q
C
Guaranteed Limits
2.0
2.0
Units
V
r
0.1
r
0.5
r
1.0
r
5.0
r
1.0
r
10
P
A
P
A
P
A
Note 4:
Measured per input. All other inputs at V
CC
or GND.
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2
Test/Measurement
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