SN74ALS131NP3 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> SN74ALS131NP3

SN74ALS131NP3: DescriptionIC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,DIP,16PIN,PLASTIC; Categorylogic logic; File Size212KB，4 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

Stay tuned Parametric Compare

SN74ALS131NP3 Overview

IC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,DIP,16PIN,PLASTIC

SN74ALS131NP3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Texas Instruments
package instruction	DIP, DIP16,.3
Reach Compliance Code	not_compliant
JESD-30 code	R-PDIP-T16
Logic integrated circuit type	OTHER DECODER/DRIVER
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Base Number Matches	1

SN74ALS131NP3 Related Products

	SN74ALS131NP3	SN74ALS131D3	SN74ALS131D	SN74ALS131N	SN74ALS131N3	SN74ALS131NP1	SN74ALS131N1
Description	IC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,DIP,16PIN,PLASTIC	IC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,SOP,16PIN,PLASTIC	IC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,SOP,16PIN,PLASTIC	IC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,DIP,16PIN,PLASTIC	IC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,DIP,16PIN,PLASTIC	IC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,DIP,16PIN,PLASTIC	IC,DECODER/DEMUX,3-TO-8-LINE,ALS-TTL,DIP,16PIN,PLASTIC
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
package instruction	DIP, DIP16,.3	SOP, SOP16,.25	SOP, SOP16,.25	DIP, DIP16,.3	DIP, DIP16,.3	DIP, DIP16,.3	DIP, DIP16,.3
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
JESD-30 code	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16	R-PDIP-T16	R-PDIP-T16	R-PDIP-T16
Logic integrated circuit type	OTHER DECODER/DRIVER	OTHER DECODER/DRIVER	OTHER DECODER/DRIVER	OTHER DECODER/DRIVER	OTHER DECODER/DRIVER	OTHER DECODER/DRIVER	OTHER DECODER/DRIVER
Number of functions	1	1	1	1	1	1	1
Number of terminals	16	16	16	16	16	16	16
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	SOP	SOP	DIP	DIP	DIP	DIP
Encapsulate equivalent code	DIP16,.3	SOP16,.25	SOP16,.25	DIP16,.3	DIP16,.3	DIP16,.3	DIP16,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	SMALL OUTLINE	SMALL OUTLINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	NO	NO	NO	NO
technology	TTL	TTL	TTL	TTL	TTL	TTL	TTL
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	THROUGH-HOLE	GULL WING	GULL WING	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Base Number Matches	1	1	1	1	1	1	1
Certification status	-	-	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified

Recommended Resources

MP4 FM radio circuit

Automatic start control circuit informed by long power outage and incoming call

Low noise amplifier circuit composed of ordinary operational amplifier

temperature controller circuit

Commutation circuit preselected by selector switch for three-phase motor

Computer motherboard circuit diagram 815 1_20

IIR Digital Filter Design - Implementing Arbitrary Order IIR Digital Filters on FPGA: [font=Verdana][font=Verdana]IIR Digital Filter Design - Implementing Arbitrary Order IIR Digital Filters on FPGA[/font][/font] Abstract: This paper introduces a method to implement arbitrary order IIR...; aimyself FPGA/CPLD

Problems with EMP injection into triodes: [color=#333333][font="][size=14px]Why for transistors, some literatures say that under EMP injection, the failure mode of transistors is BE junction short circuit, but some literatures say that BC jun...; xmxxwyh Analog electronics

Ask a simple VHDL question, the signal line is assigned an initial value: I have an IO port P from a CPLD. I want it to be in a certain state (e.g. 0) when it is powered on. After it starts working, another signal S1, S2 triggers the state change of P. For example, P is 0 w...; sioca FPGA/CPLD

USB short body patch specification diagram useful take away: USB short body patch specification diagram...; qwqwqw2088 PCB Design

I don't know how to do the homework assigned by the teacher today. Can anyone give me some advice?: Experiment 3 Priority inheritance 1 Experimental purpose Master the strategy of embedded real-time operating system ?C/OS-II to solve priority inversion - the principle of priority inheritance. 2 Prin...; sanny777 Embedded System

What does the asterisk mean in Tiantong core material?: What do the asterisks in the picture mean?...; kankelo RF/Wirelessly

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components