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HI-8482PSTF

Description
DUAL LINE RECEIVER, CQCC20
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size138KB,10 Pages
ManufacturerHolt Integrated Circuits
Websitehttp://www.holtic.com/
Environmental Compliance
Related ProductsFound3parts with similar functions to HI-8482PSTF
Download Datasheet Parametric View All

HI-8482PSTF Overview

DUAL LINE RECEIVER, CQCC20

HI-8482PSTF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerHolt Integrated Circuits
Parts packaging codeSOIC
package instructionSOP,
Contacts20
Reach Compliance Codecompli
ECCN code7A994
Other featuresALSO OPERATES AT +/-15 V SUPPLY
Differential outputNO
Input propertiesDIFFERENTIAL SCHMITT TRIGGER
Interface integrated circuit typeLINE RECEIVER
Interface standardsARINC 429
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length12.789 mm
Humidity sensitivity level1
Nominal negative supply voltage-12 V
Number of functions2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)250
Certification statusNot Qualified
Maximum receive delay
Number of receiver bits2
Maximum seat height2.82 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
Supply voltage 1-max13.2 V
Mains voltage 1-minute10.8 V
Supply voltage1-Nom12 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width7.52 mm
HI-8482
August 2006
ARINC 429 DUAL LINE RECEIVER
GENERAL DESCRIPTION
The HI-8482 bus interface unit is a silicon gate CMOS de-
vice designed as a dual differential line receiver in accor-
dance with the requirements of the ARINC 429 bus speci-
fication. The device translates incoming ARINC 429 sig-
nals to normal CMOS/TTL levels on each of its two inde-
pendent receive channels. The HI-8482 is also function-
ally equivalent to the Fairchild/Raytheon RM3183.
The self-test inputs force the outputs to either a ZERO,
ONE, or NULL state for system tests. While in self-test
mode, the ARINC inputs are ignored.
All the ARINC inputs have built-in hysteresis to reject
noise that may be present on the ARINC bus. Additional
input noise filtering can also be accomplished with exter-
nal capacitors.
The HI-8482 line receiver is one of several options of-
fered by Holt Integrated Circuits to interface to the ARINC
bus. The digital data processing for serial-to-parallel con-
version and clock recovery can be accomplished with the
HI-6010, HI-8683 or similar devices.
The HI-8482 is available in a variety of ceramic & plastic
packages including Small Outline (SOIC), J-Lead PLCC,
Cerquad, DIP & Leadless Chip Carrier (LCC).
PIN CONFIGURATIONS
(Top Views)
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
HI-8482J
HI-8482JT
20 - PIN
PLASTIC
J-LEAD PLCC
+V
L
- 9
N/C - 10
OUT1B - 12
+V
S
- 11
20 - TESTB
3 - CAP2B
2 - TESTA
1 - -V
S
N/C - 13
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +V
S
FEATURES
!
Converts ARINC 429 levels to digital data
!
Direct replacement for the RM3183
!
Greater than 2 volt receiving hysteresis
!
TTL and CMOS outputs and test inputs
!
Military screening available
!
20-Pin SOIC, PLCC, CERQUAD, DIP &
LCC packages are available
-V
S
- 1
TESTA - 2
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
+V
L
- 9
N/C - 10
HI-8482PSI
HI-8482PST
20 - PIN
PLASTIC
SMALL
OUTLINE
(SOIC) - WB
(See page 6 for additional Package Pin Configurations)
TRUTH TABLE
ARINC INPUTS
V (A) - V (B)
Null
Zero
One
Don't Care
Don't Care
Don't Care
TEST INPUTS
TEST A
0
0
0
0
1
1
OUTPUTS
OUT A
0
0
1
0
1
0
TEST B
0
0
0
1
0
1
OUT B
0
1
0
1
0
0
(DS8482 Rev. F)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/06

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