XR19L400
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
JULY 2009
REV. 1.0.3
GENERAL DESCRIPTION
The XR19L400 (L400) is a highly integrated device that
combines a full-featured single channel Universal
Asynchronous Receiver and Transmitter (UART) and RS-
485 transceivers. The L400 is designed to operate with a
single 3.3V or 5V power supply. The L400 is fully compliant
with RS-485 Standards.
The L400 operates in four different modes: Active, Partial
Sleep, Full Sleep and Power-Save. Each mode can be
invoked via hardware or software. Upon power-up, the
L400 is in the Active mode where the UART and RS-485
transceiver function normally. In the Partial Sleep mode, the
internal crystal oscillator of the UART or charge pump of the
RS-485 transceiver is turned off. In Full Sleep mode, both
the crystal oscillator and the charge pump are turned off.
While the UART is in the Sleep mode, the Power-Save
mode isolates the core logic from the control signals (chip
select, read/write strobes, address and data bus lines) to
minimize the power consumption. The RS-485 receivers
remain active in any of these four modes.
APPLICATIONS
•
Battery-Powered Equipment
•
Handheld and Mobile Devices
•
Handheld Terminals
•
Industrial Peripheral Interfaces
•
Point-of-Sale (POS) Systems
FEATURES
•
Meets true RS-485 standards at 3.3V or 5V operation
•
Up to 8 Mbps data transmission rate
•
45us sleep mode exit (charge pump to full power)
•
ESD protection for RS-485 I/O pins at
■
■
■
+/-15kV - Human Body Model
+/- 8kV - IEC 61000-4-2, Contact Discharge
+/- 15kV - IEC 61000-4-2, Air-Gap Discharge
•
Software compatible with industry standard 16550 UART
•
Intel/Motorola bus select
•
Complete modem interface
•
Sleep and Power-save modes to conserve battery power
•
Wake-up interrupt upon exiting low power modes
F
IGURE
1. B
LOCK
D
IAGRAM
VCC33
XTAL1
XTAL2
R_EN
GND
VCC50
ACP
C1+
*5 V Tolerant
Inputs
Intel or Motorola Bus Interface
PwrSave
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CS# (CS#)
INT (IRQ#)
RESET (RESET#)
I/M#
HALF/FULL#
Crystal
Osc/Buffer
BRG
Charge Pump
TX+
TX-
RX+
RX-
VCC33
64 Byte
TX FIFO
UART Registers
64 Byte
RX FIFO
TX
RX
CTS#
Modem
I/Os
DSR#
RI#
CD#
RS-485 Transceiver
XR19L400
UART
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
C1-
XR19L400
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
F
IGURE
2. P
IN
O
UT OF THE
D
EVICE
REV. 1.0.3
34 HALF/FULL#
33 VCC50
32 TXA+
36 TEST1
35 TEST0
D0
D1
D2
D3
D4
D5
D6
D7
31 GND
37 INT
40 A0
39 A1
38 A2
1
2
3
4
5
6
7
30
29
28
TXA-
NC
RXA+
RXA-
C1+
C1-
NC
NC
NC
VCC33
XR19L 400
40 - pin QFN
Intel Bus Mode
27
26
25
24
23
22
21
R_EN 20
8
CS# 9
TEST2 10
POWERSAVE 11
RESET 18
ACP 19
XTAL1 12
IOW# 14
IOR# 15
NC 16
XTAL2 13
I/M# 17
VCC
34 HALF/FULL#
33 VCC50
32 TXA+
36 TEST1
35 TEST0
37 IRQ#
D0
D1
D2
D3
D4
D5
D6
D7
CS#
31 GND
40 A0
39 A1
38 A2
1
2
3
4
5
6
7
8
9
RESET# 18
ACP 19
XTAL1 12
POWERSAVE 11
XTAL2 13
R_EN 20
R/W# 14
NC 15
NC 16
I/M# 17
30
29
28
TXA-
NC
RXA+
RXA-
C1+
C1-
NC
NC
NC
VCC33
XR19L400
40-pin QFN
Motorola Bus Mode
27
26
25
24
23
22
21
TEST2 10
GND
ORDERING INFORMATION
P
ART
N
UMBER
XR19L400IL40
P
ACKAGE
40-pin QFN
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
D
EVICE
S
TATUS
Active
2
XR19L400
REV. 1.0.3
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
PIN DESCRIPTIONS
Pin Descriptions
N
AME
40-QFN
PIN#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(NC)
38
39
40
8
7
6
5
4
3
2
1
15
I
Address bus lines [2:0]. These 3 address lines select one of the internal registers in the
UART during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe
(active LOW). The falling edge instigates the internal write cycle and the rising edge trans-
fers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
This input is the chip select (active low) for the UART in both the Intel and Motorola bus
modes.
IOW#
(R/W#)
14
I
CS#
(CS#)
INT
(IRQ#)
9
37
I
O When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
(OD) HIGH interrupt output. This output is enabled through the software setting of MCR[3]. This
output is set to the active mode when MCR[3] is set to a logic 1, and set to the three state
mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output for both channels. An external pull-up resistor is required
for proper operation. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
SERIAL I/O INTERFACE (RS-485/RS-485 Voltage Levels)
TX+
TX-
RX+
RX-
32
30
28
27
O
I
Differential UART Transmit Data.
Differential UART Receive Data.
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
HALF/
FULL#
34
I
Half-duplex or full-duplex mode select. This pin is sampled upon power-up.
When HALF/FULL# is HIGH, half-duplex mode is enabled.
When HALF/FULL# is LOW, full-duplex mode is enabled.
After power-up, FCTR bit-3 can select between the half-duplex or full-duplex modes.
Crystal or external clock input.
XTAL1
12
I
3
XR19L400
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
Pin Descriptions
N
AME
XTAL2
PwrSave
ACP
40-QFN
PIN#
13
11
19
T
YPE
O
I
I
Crystal or buffered clock output.
Power-Save (active high). This feature isolates the L400’s data bus interface from the host
preventing other bus activities that cause higher power drain during sleep mode.
Autosleep for Charge Pump (active HIGH). When the power supply is 3.3V, this pin shuts off
the charge pump if the UART is already in sleep mode, i.e. the XTAL2 output is LOW. When
the power supply is 5V, this pin should be connected to GND.
Intel or Motorola Bus Select.
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period.
Charge pump capacitors. As shown in
Figure 1
, a 0.22 uF capacitor should be placed
between these 2 pins.
Regulator Enable. This pin regulates the 5V VCC down to 3.3V internally for the UART.
When the supply voltage is 3.3V, connect R_EN to GND.
When the supply voltage is 5V, connect R_EN to VCC.
Factory Test Modes. For normal operation, these pins must be connected to GND.
D
ESCRIPTION
REV. 1.0.3
I/M#
17
I
RESET
(RESET#)
18
I
C1-
C1+
R_EN
25
26
20
-
I
TEST0
TEST1
TEST2
VCC33
35
36
10
21
I
I
I
Pwr 3.3V power supply. When VCC33 is used, R_EN pin should be connected to GND.
A 0.1 uF capacitor to GND is recommended on this power supply pin. If VCC33 is not used
as the power supply pin, VCC33 should be left unconnected. See
Figure 3
. All CMOS/
TTL input pins, except XTAL1, are 5V tolerant.
Pwr 5.0V power supply. When VCC50 is used, R_EN pin should be connected to VCC.
A 1uF capacitor to GND is recommended on the VCC50 power supply pin. The 1uF capac-
itor is recommended whether VCC33 or VCC50 is used as the power supply pin. See
Figure 3
. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
Pwr Power supply common, ground.
Pwr The center pad on the backside of the QFN package is metallic and is not electrically con-
nected to anything inside the device. It must be soldered on to the PCB and may be option-
ally connected to GND on the PCB. The thermal pad size on the PCB should be the
approximate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
-
No Connect. Note that in Motorola mode, the IOR# pin also becomes an NC pin.
VCC50
33
GND
-
31
PAD
NC
16, 22, 23,
24, 29
N
OTE
:
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH" indicates a voltage in the range VIH to VCC.
4
XR19L400
REV. 1.0.3
SINGLE CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
F
IGURE
3. R
ECOMMENDED
3.3V
OR
5V P
OWER
S
UPPLY
C
ONNECTIONS
3.3V Power Supply
5V Power Supply
VCC50
1 uF
GND
3.3V
0.1 uF
GND
5V
1 uF
GND
VCC50
VCC33
VCC33
R_EN
GND
R_EN
5
京公网安备 11010802033920号
EEWORLD
