70V5388S133BGG8 datasheet, PDF

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70V5388S133BGG8: DescriptionMulti-Port SRAM, 64KX18, 3.4ns, CMOS, PBGA272; Categorystorage storage; File Size248KB，29 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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70V5388S133BGG8 Overview

Multi-Port SRAM, 64KX18, 3.4ns, CMOS, PBGA272

70V5388S133BGG8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
package instruction	BGA-272
Reach Compliance Code	compliant
Maximum access time	3.4 ns
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	S-PBGA-B272
JESD-609 code	e3
memory density	1179648 bit
Memory IC Type	FOUR-PORT SRAM
memory width	18
Number of functions	1
Number of ports	4
Number of terminals	272
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA272,20X20,50
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum standby current	0.015 A
Minimum standby current	3.15 V
Maximum slew rate	0.32 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
Base Number Matches	1

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3.3V 64/32K X 18

SYNCHRONOUS

FOURPORT™ STATIC RAM

Features

◆

IDT70V5388/78

◆

True four-ported memory cells which allow simultaneous

access of the same memory location

Synchronous Pipelined device

– 64/32K x 18 organization

Pipelined output mode allows fast 200MHz operation

High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x

4 ports)

LVTTL I/O interface

High-speed clock to data access 3.0ns (max.)

3.3V Low operating power

Interrupt flags for message passing

Width and depth expansion capabilities

Counter readback on address lines

U B

C E

0P1

1P1

L B

O E

◆

Counter wrap-around control

– Internal mask register controls counter wrap-around

– Counter-Interrupt flags to indicate wrap-around

Mask register readback on address lines

Global Master reset for all ports

Dual Chip Enables on all ports for easy depth expansion

Separate upper-word and lower-word controls on all ports

272-BGA package (27mm x 27mm 1.27mm ball pitch) and

256-BGA package (17mm x 17mm 1.0mm ball pitch)

Commercial and Industrial temperature ranges

JTAG boundary scan

MBIST (Memory Built-In Self Test) controller

Green parts available, see ordering information

Port - 1 Logic Block Diagram

(2)

1 /0

I/O

9P1

- I/O

17P1

I/O

0P1

- I/O

8P1

Port 1

I/O

Control

TR S T

TMS

TCK

TDI

CLKMBIST

JTAG

Controller

MBIST

TDO

Addr.

Read

Back

Port 1

Readback

MRST

0P1

- A

15P1

(1)

C N T R D

M K R D

M K L D

C N T IN C

C N T L D

C N T R S T

CLK

MRST

C N T IN T

Port 1

Mask

Priority

Decision

Logic

Port 1

Counter/

Address

Port 1

Address

Decode

64KX18

Memory

Array

C E

0P1

1P1

CLK

Port 1

Interrupt

Logic

IN T

MRST

NOTE:

1. A

x is a NC for IDT70V5378.

2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.

5649 drw 01

JANUARY 2006

DSC-5649/4

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