Features
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Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
Data Sheet Describes Mode 0 Operation
Low-voltage Operation
– 1.8 (V
CC
= 1.8V to 3.6V)
10 MHz Clock Rate (2.7
−
3.6V)
128-byte Page Mode and Byte Write Operation Supported
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (5 ms Max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >40 Years
Automotive Grade Temperature Available
Lead-free/Halogen-free Devices
8-lead JEDEC SOIC, 8-lead TSSOP and 8-lead SAP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Die
SPI Serial
EEPROM
512K (65,536 x 8)
AT25512
Description
The AT25512 provides 524,288 bits of serial electrically-erasable programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device
is optimized for use in many industrial and commercial applications where low-power
and low-voltage operation are essential. The devices are available in space saving
8-lead JEDEC SOIC, 8-lead TSSOP and 8-lead SAP packages. In addition, the
entire family is available in 1.8V (1.8V to 3.6V) versions.
The AT25512 is enabled through the Chip Select pin (CS) and accessed via a 3-wire
interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All programming cycles are completely self-timed, and no separate
Erase cycle is required before Write.
Table 1.
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
CS
SO
WP
GND
CS
SO
WP
GND
Advance
Information
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
VCC
HOLD
SCK
SI
8-lead SAP
8
7
6
5
1
2
3
4
CS
SO
WP
GND
Bottom View
5165A–SEEPR–1/07
1
Block Write protection is enabled by programming the status register with top ¼, top ½
or entire array of write protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware data protection is pro-
vided via the WP pin to protect against inadvertent write attempts to the status register.
The HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature
.........................................−65°C
to +150°C
Voltage on Any Pin
with Respect to Ground
........................................ −1.0V
to +5.0V
Maximum Operating Voltage ............................................ 4.3V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Figure 1.
Block Diagram
65536x 8
Table 2.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +3.6V (unless otherwise noted)
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
2
AT25512
5165A–SEEPR–1/07
AT25512
Table 3.
DC Characteristics
Applicable over recommended operating range from T
AI
=
−
40°C to +85°C, V
CC
= +1.8V to +3.6V,
V
CC
= +1.8V to +3.6V(unless otherwise noted)
Symbol
V
CC1
I
CC1
I
CC2
I
SB1
I
SB2
I
SB3
I
IL
I
OL
V
IL(1)
V
IH(1)
V
OL1
V
OH1
Note:
Parameter
Supply Voltage
Supply Current
Supply Current
Standby Current
Standby Current
Standby Current
Input Leakage
Output Leakage
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
1.8V
≤
V
CC
≤
3.6V
I
OL
= 0.15 mA
I
OH
=
−100
µA
V
CC
−0.2
V
CC
= 3.6V at 10 MHz,
SO = Open, Read, Write
V
CC
= 3.6V at 1 MHz,
SO = Open, Read, Write
V
CC
= 1.8V, CS = V
CC
V
CC
= 2.7V, CS = V
CC
V
CC
= 3.6V, CS = V
CC
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
, T
AC
= 0°C to 70°C
−3.0
−3.0
−1.0
V
CC
x 0.7
Test Condition
Min
1.8
5.0
2.2
0.2
0.5
2.0
Typ
Max
3.6
7.0
3.5
3.0
3.0
5.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.2
Units
V
mA
mA
µA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
Table 4.
AC Characteristics
Applicable over recommended operating range from T
AI
=
−
40°C to + 85°C, V
CC
= As Specified, CL = 1 TTL Gate and 30 pF
(unless otherwise noted)
Symbol
f
SCK
t
RI
t
FI
t
WH
t
WL
t
CS
t
CSS
t
CSH
t
SU
Parameter
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
CS Setup Time
CS Hold Time
Data In Setup Time
Voltage
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
40
80
40
80
100
200
100
200
100
200
10
20
Min
0
0
Max
10
5
2
2
2
2
Units
MHz
µs
µs
ns
ns
ns
ns
ns
ns
3
5165A–SEEPR–1/07
Table 4.
AC Characteristics (Continued)
Applicable over recommended operating range from T
AI
=
−
40°C to + 85°C, V
CC
= As Specified, CL = 1 TTL Gate and 30 pF
(unless otherwise noted)
Symbol
t
H
t
HD
t
CD
t
V
t
HO
t
LZ
t
HZ
t
DIS
t
WC
Endurance
(1)
Note:
Parameter
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
Output Hold Time
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Write Cycle Time
3.3V, 25°C, Page Mode
Voltage
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
2.7−3.6
1.8−3.6
1M
Min
10
20
10
20
10
20
0
0
0
0
0
0
50
100
50
100
50
100
5
5
40
80
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write Cycles
1. This parameter is ensured by characterization only.
Serial Interface
Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the serial clock pin (SCK) is always an input, the AT25512 always
operates as a slave.
TRANSMITTER/RECEIVER:
The AT25512 has separate pins designated for data
transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the
AT25512, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT:
The AT25512 is selected when the CS pin is low. When the device is
not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS pin to select the AT25512.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
4
AT25512
5165A–SEEPR–1/07
AT25512
WRITE PROTECT:
The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25512 in a system with the WP pin tied to ground and still be able to
write to the status register. All WP pin functions are enabled when the WPEN bit is set to
“1”.
Figure 2.
SPI Serial Interface
AT25512
5
5165A–SEEPR–1/07
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