Features
•
MPEG I/II-Layer 3 Hardwired Decoder
– Stand-alone MP3 Decoder
– 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency
– Separated Digital Volume Control on Left and Right Channels (Software Control
using 31 Steps)
– Bass, Medium, and Treble Control (31 Steps)
– Bass Boost Sound Effect
– Ancillary Data Extraction
– CRC Error and MPEG Frame Synchronization Indicators
20-bit Stereo Audio DAC
– 93 dB SNR Playback Stereo Channel
– 32 Ohm/ 20 mW Stereo Headset Drivers
– Stereo Line Level Input, Differential Mono Auxiliary Input
Programmable Audio Output for Interfacing with External Audio System
– I
2
S Format Compatible
Mono Audio Power Amplifier
– 440mW on 8 Ohms Load
USB Rev 1.1 Controller
– Full Speed Data Transmission
Built-in PLL
– MP3 Audio Clocks
– USB Clock
MultiMediaCard
®
Interface, Secure Digital Card Interface
Standard Full Duplex UART with Baud Rate Generator
Power Management
– Power-on Reset
– Idle Mode, Power-down Mode
Operating Conditions:
– 2.7 to 3V,
±10%,
25 mA Typical Operating at 25°C
– 37 mA Typical Operating at 25°C Playing Music on Earphone
– Temperature Range: -40°C to +85°C
– Power Amplifier Supply 3.2V to 5.5V
Packages
– CTBGA 100-pin
•
•
•
•
•
•
•
•
•
Single-Chip MP3
Decoder with
Full Audio
Interface
AT83SND2CMP3
AT83SND2CDVX
Preliminary
•
Typical
Applications
•
•
•
•
•
•
MP3-Player
PDA, Camera, Mobile Phone MP3
Car Audio/Multimedia MP3
Home Audio/Multimedia MP3
Toys
Industrial Background Music / Ads
Rev. 7524B–MP3–05/06
Description
The AT83SND2CMP3 has been developped as a versatile remote controlled MP3
player for very fast MP3 feature implementation into most existing system. It perfectly
fits features needed in mobile phones and toys, but can also be used in any portable
equipment and in industrial applications.
Audio files and any other data can be stored in a Nand Flash memory or in a removable
Flash card such as MultiMediaCard (MMC) or Secure Digital Card (SD). Music collec-
tions are very easy to build, as data can be stored using the standard FAT12/16 and
FAT32 file system.
Thanks to the USB port, data can be transferred and maintained from and to any com-
puter based on Windows
®
, Linux
®
and Mac OS
®
.
File system is controlled by the AT83SND2CMP3 so the host controller does not have to
handle it.
In addition to the USB device port, the MP3 audio system can be connected to any
embedded host through a low cost serial link UART. Host controller can fully remote
control the MP3 decoder behaviour using a command protocol over the serial link.
File system is controlled by the AT83SND2CMP3 so host controller does not have to
handle it.
Files can also be uploaded or dowloaded from host environment to NAND Flash or
Flash Card.
2
AT83SND2CMP3
7524B–MP3–05/06
AT83SND2CMP3
1. Block Diagram
Figure 2.
Block Diagram
VDD
VSS UVDD UVSS
FILT
X1
X2
RST
3
Clock and PLL
Unit
Control Unit
Interrupt
Handler Unit
INT0
INT1
3
D+
D-
USB
Controller
I/OPorts
X1
X2
P0-P4
MP3
Decoder
Unit
Keyboard
Interface
DOUT
DCLK
DSEL
SCLK
KIN0
I
2
S/PCM
Audio
Interface
UART
and
BRG
3
3
TXD
RXD
Timers 0/1
Watchdog
3
3
T0
T1
HSR
HSL
AUXP
AUXN
LINEL
LINER
MONOP
MONON
MCLK
Audio
DAC
SD / MMC
Interface
MDAT
PAINP
PAINN
HPP
HPN
Audio
PA
MCMD
3
Alternate function of Port 3
4
Alternate function of Port 4
3
7524B–MP3–05/06
Pin Description
Pinouts
Figure 3.
AT83SND2CMP3 100-pin BGA Package
10
NC
9
NC
8
P2.0/
A8
7
P4.1/
6
VDD
5
VSS
4
NC
3
AUXP
2
AUXN
1
NC
A
B
C
D
E
F
G
H
J
K
VDD
P2.2/
A10
P2.1/
A9
P4.0/
P4.2/
MONON
MONOP
P0.0/
AD0
KIN0
NC
P2.4/
A12
P2.3/
A11
P2.5/
A13
P4.3/
P0.6/
AD6
P0.4/
AD4
P0.3/
AD3
P0.2/
AD2
P0.1/
AD1
NC
P2.6/
A14
P2.7/
A15
MCLK
NC
P0.7/
AD7
P0.5/
AD5
NC
NC
NC
NC
NC
VSS
VDD
ESDVSS
VDD
SDA
AUDVREF
SCL
HSL
AUDVDD
MCMD
MDAT
NC
P3.2/
INT0
P3.1/
TXD
VSS
FILT
PVDD
HSR
HSVDD
RST
AUDRST
SCLK
DSEL
P3.4/
T0
P3.0/
RXD
LINER
LINEL
PVSS
HSVSS
NC
VSS
DOUT
DCLK
P3.5/
T1
TST
X1
X2
INGND
AUDVSS
VDD
AUDVSS
CBP
LPHN
P3.7/
RD
P3.6/
WR
VSS
D-
D+
AUDVCM
PAINP
PAINN
HPP
AUDVBAT
HPN
AUDVSS
P3.3/
INT1
VDD
UVDD
UVSS
1. NC = Do Not Connect
4
AT83SND2CMP3
7524B–MP3–05/06
AT83SND2CMP3
Signals
All the AT83SND2CMP3 signals are detailed by functionality in following tables.
Table 1.
Ports Signal Description
Signal
Name
Type
Description
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To
avoid any parasitic current consumption, floating P0 inputs must be
polarized to V
DD
or V
SS
.
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
Alternate
Function
P0.7:0
I/O
AD7:0
P2.7:0
I/O
A15:8
RXD
TXD
P3.7:0
I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
INT0
INT1
T0
T1
WR
RD
P4.3:0
I/O
Port 4
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
Table 2.
Clock Signal Description
Signal
Name
Type
Description
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
Alternate
Function
X1
I
-
X2
O
-
FILT
I
-
Table 3.
Timer 0 and Timer 1 Signal Description
Signal
Name
Type
Description
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
INT0
I
External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set,
bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is
set by a low level on INT0#.
P3.2
Alternate
Function
5
7524B–MP3–05/06
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