552BE000205BG datasheet, PDF - EEWORLD Datasheet

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552BE000205BG: DescriptionLVDS Output Clock Oscillator, 155.52MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size4MB，80 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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552BE000205BG Overview

LVDS Output Clock Oscillator, 155.52MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

552BE000205BG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	IT CAN ALSO OPERATE AT 38.880000 MHZ
Maximum control voltage	3.3 V
Minimum control voltage
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	25 ppm
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	552
Installation features	SURFACE MOUNT
Nominal operating frequency	155.52 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	177.8mm x 127.0mm x 41.91mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

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Si552

U A L

R E Q U E N C Y

VCXO (10 M H

Z T O

1.4 GH

)

Features

Available with any-rate output

frequencies from 10–945 MHz and

select frequencies to 1.4 GHz

Two selectable output frequencies

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL, LVDS

& CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Applications

SONET/SDH

xDSL

10 GbE LAN / WAN

Low-jitter clock generation

Optical Modules

Clock and data recovery

Ordering Information:

See page 7.

Description

The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced

DSPLL

circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and select frequencies to 1400 MHz. Unlike traditional VCXO’s where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low jitter clocks in noisy environments typically found in communication

systems. The Si552 IC based VCXO is factory configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

Pin Assignments:

See page 6.

(Top View)

GND

CLK–

CLK+

Functional Block Diagram

CLK- CLK+

Fixed

Frequency XO

Any-rate

10–1400 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 0.5 7/06

Si552

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