IDT72291L20TFI9 datasheet, PDF

Datasheet> All Categories > storage> storage> IDT72291L20TFI9

IDT72291L20TFI9: DescriptionFIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, STQFP-64; Categorystorage storage; File Size272KB，26 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric View All

IDT72291L20TFI9 Overview

FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, STQFP-64

IDT72291L20TFI9 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	STQFP-64
Contacts	64
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	12 ns
Other features	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
period time	20 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	10 mm
memory density	1179648 bit
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	10 mm
Base Number Matches	1

Preview

Download Datasheet

View All

CMOS SuperSync FIFO™

65,536 x 9

131,072 x 9

FEATURES:

•

IDT72281

IDT72291

•

Choose among the following memory organizations:

IDT72281

65,536 x 9

IDT72291

131,072 x 9

Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs

10ns read/write cycle time (6.5ns access time)

Fixed, low first word data latency time

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable

settings

Retransmit operation with fixed, low first word data

latency time

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

Program partial flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or First

Word Fall Through timing (using

and

flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

Independent Read and Write clocks (permit reading and writing

simultaneously)

Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

High-performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

DESCRIPTION:

The IDT72281/72291 are exceptionally deep, high speed, CMOS First-In-

First-Out (FIFO) memories with clocked read and write controls. These FIFOs

offer numerous improvements over previous SuperSync FIFOs, including the

following:

•

The limitation of the frequency of one clock input with respect to the other has

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

•

The period required by the retransmit operation is now fixed and short.

•

The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is now fixed and short. (The variable

clock cycle counting delay associated with the latency period found on

previous SuperSync devices has been eliminated on this SuperSync family.)

SuperSync FIFOs are particularly appropriate for network, video, telecom-

munications, data communications and other applications that need to buffer

large amounts of data.

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK

-D

LD SEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

WRITE CONTROL

LOGIC

RAM ARRAY

65,536 x 9

131,072 x 9

FLAG

LOGIC

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

-Q

4675 drw01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



2002

SEPTEMBER 2002

DSC-4675/3

Recommended Resources

Remote control TV doorbell reception and alarm circuit

Electronic ballast circuit diagram using L6569

TL494 internal equivalent circuit diagram

The most practical basic diagram circuit 41-motor starting circuit

Double pulse generator circuit

Soft start circuit using transistors

Ask the moderator a question about the external clock of STM32's TIMx.: I want to use channel 3 of STM32's TIM3 as a counter to count the number of external pulses. I want to send the external pulses as an external clock to channel 3 of TIM3. However, looking at the block...; weipingid stm32/stm8

Power supply test analysis manual worth reading for both veterans and novices: Good information, as the title suggests!...; 欧木木 Power technology

[CH554 Review] Part 4 Peripherals, I2C Interface OLED LCD Driver: [i=s]This post was last edited by yang_alex on 2017-11-6 13:21[/i] The previous three articles talked about the development environment of CH554. Now let's talk about the application of CH554. When it...; yang_alex MCU

USB host stack acceptance test: The USB host stack is outsourced to a company, which mainly includes Audio class, Mass storage class, and HID class driver. I would like to ask how to conduct acceptance and how to conduct acceptance ...; ft1826119 Embedded System

I mentioned before that I would print the 4 brothers + Master Mouse of [Ninja Turtles] and now I have released the first photo: I posted one of the brothers in Teenage Mutant Ninja Turtles 4 before, but nothing happened. It's not a bad ending. I was thinking about the other three characters and Master Mouse. Let me post a phot...; cardin6 Creative Market

Shenzhen Huaqiangbei Electronics Market was closed urgently, and merchants picked up their goods overnight: From 0:00 to 24:00 on March 2, 25 new cases were reported in Shenzhen. According to preliminary epidemiological investigation, the main activity tracks of the new cases in recent days involved Shenzhe...; 赵玉田 Talking

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components