ZNBG2000
ZNBG2001
FET BIAS CONTROLLER
DEVICE DESCRIPTION
The ZNBG series of devices are designed to meet the
bias requirements of GaAs and HEMT FETs
commonly used in satellite receiver LNBs, PMR,
cellular telephones etc. with a minimum of external
components.
With the addition of two capacitors and a resistor the
devices provide drain voltage and current control for
2 external grounded source FETs, generating the
regulated negative rail required for FET gate biasing
whilst operating from a single supply. This negative
bias, at -3 volts, can also be used to supply other
external circuits.
The ZNBG2000/1 contains two bias stages. A single
resistor allows FET drain current to be set to the
desired level. The series also offers the choice of
drain voltage to be set for the FETs, the ZNBG2000
gives 2.2 volts drain whilst the ZNBG2001 gives 2
volts.
These devices are unconditionally stable over the full
working temperature with the FETs in place, subject
to the inclusion of the recommended gate and drain
capacitors. These ensure RF stability and minimal
injected noise.
It is possible to use less than the devices full
complement of FET bias controls, unused drain and
gate connections can be left open circuit without
affecting operation of the remaining bias circuits.
In order to protect the external FETs the circuits have
been designed to ensure that, under any conditions
including power up/down transients, the gate drive
from the bias circuits cannot exceed the range -3.5V
to 0.7V. Furthermore if the negative rail experiences a
fault condition, such as overload or short circuit, the
drain supply to the FETs will shut down avoiding
excessive current flow.
The ZNBG2000/1 are available in MSOP10 packages
for the minimum in devices size. Device operating
temperature is -40 to 80°C to suit a wide range of
environmental conditions.
FEATURES
•
Provides bias for GaAs and HEMT FETs
•
Drives up to two FETs
•
Dynamic FET protection
•
Drain current set by external resistor
•
Regulated negative rail generator requires only 2
external capacitors
APPLICATIONS
•
Satellite receiver LNBs
•
Private mobile radio (PMR)
•
Single in single out C Band LNB
•
Cellular telephones
•
Choice in drain voltage
•
Wide supply voltage range
•
MSOP surface mount package
ISSUE 1 - AUGUST 2001
1
ZNBG2000
ZNBG2001
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Supply Current
Drain Current (per FET)
(set by R
CAL1
and R
CAL2
)
-0.6V to 15V
100mA
0 to 15mA
Output Current
Operating Temperature
Storage Temperature
100mA
-40 to 80°C
-40 to 85°C
500mW
Power Dissipation (T
amb 25 C)
MSOP10
ELECTRICAL CHARACTERISTICS TEST CONDITIONS (Unless otherwise
SYMBOL PARAMETER
CONDITIONS
Min
V
CC
I
CC
V
SUB
E
ND
E
NG
f
O
Supply Voltage
Supply Current
Substrate Voltage
(Internally generated)
Output Noise
Drain Voltage
Gate Voltage
Oscillator Freq.
I
D1
and I
D2=0
I
D1
and I
D2
=10mA
I
SUB
= 0
I
SUB
= -200µA
C
G
=4.7nF, C
D
=10nF
C
G
=4.7nF, C
D
=10nF
150
330
-3.5
5
5
24
-2.8
LIMITS
Typ
Max
12
10
30
-2
-2
0.02
0.005
800
UNITS
V
mA
mA
V
V
Vpkpk
Vpkpk
kHz
DRAIN CHARACTERISTICS
I
DO
I
D
I
DV
I
DT
V
D
Output Current Range
Current
Current Change
with V
CC
with T
j
Voltage
V
CC
=5 to 12V
T
j
=-40 to +80°C
ZNBG2000 I
D1
and I
D2
=10mA
ZNBG2001
2
1.8
0.5
0.05
2.2
2
2.4
2.2
%/V
%/°C
V
V
Set by R
CAL1
0
8
10
15
12
mA
mA
Voltage Change
V
DV
V
DT
with V
CC
with T
j
V
CC
= 5 to 12V
T
j
= -40 to +80°C
0.5
50
%/V
ppm
GATE CHARACTERISTICS
I
GO
V
OL
Output Current Range
Output Voltage
Output Low
I
D1
IG1
and I
D2
=12mA
and I
G2
=0
-3.5
-3.5
0.4
-2
-2
1
V
V
V
-40
2000
µA
I
D1
and I
D2
=12mA
I
G1
and I
G2
= -10µA
V
OH
Output High
I
D1
and I
D2
= 8mA
I
G1
and I
G2
= 0
Notes:
1. The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, C
NB
and C
SUB
, of 47nF are required for this
purpose.
2. The characteristics are measured using an external reference resistors R
CAL1
of value 16kΩ wired from pin R
CAL1
to ground.
3. Noise voltage is not measured in production.
4. Noise voltage measurement is made with FETs and gate and drain capacitors in place on all outputs. C
G
, 4.7nF, are connected between gate outputs and
ISSUE 1 - AUGUST 2001
2
ZNBG2000
ZNBG2001
TYPICAL CHARACTERISTICS
16
Vcc = 5V
Drain Current (mA)
14
12
10
8
6
4
2
0
0
10
20
30
40
50
0.0
-0.5
Note:- Operation with loads > 200µA
is not guaranteed.
Vsub (V)
-1.0
-1.5
-2.0
-2.5
-3.0
0
0.2
Vcc = 5V
6V
8V
10V
0.4
0.6
0.8
1.0
Rcal (k)
External Vsub Load (mA)
JFET Drain Current v Rcal
Vsub v External Load
2.4
ZNBG2000
2.2
ZNBG2001
Drain Voltage (V)
2.3
Drain Voltage (V)
2.1
2.2
Vcc = 5V
6V
8V
10V
2.0
Vcc = 5V
6V
8V
10V
2.1
1.9
2.0
2
4
6
8
10
12
14
16
1.8
2
4
6
8
10
12
14
16
Drain Current (mA)
Drain Current (mA)
JFET Drain Voltage v Drain Current
JFET Drain Voltage v Drain Current
5
ISSUE 1 - AUGUST 2001
3
ZNBG2000
ZNBG2001
FUNCTIONAL DIAGRAM
FUNCTIONAL
DESCRIPTION
The ZNBG devices provide all the bias requirements
for external FETs, including the generation of the
negative supply required for gate biasing, from the
single supply voltage.
The diagram above shows a single stage from the
ZNBG series. The ZNBG2000/1 contains 2 such
stages.
The drain voltage of the external FET Q
N
is set by the
ZNBG device to its normal operating voltage. This is
determined by the on board V
D
Set reference, for the
ZNBG2000 this is nominally 2.2 volts whilst the
ZNBG2001 provides nominally 2 volts.
The drain current taken by the FET is monitored by
the low value resistor I
D
Sense. The amplifier driving
the gate of the FET adjusts the gate voltage of Q
N
so
that the drain current taken matches the current
called for by an external resistor R
CAL
. Both ZNBG
devices have the facility to program different drain
currents into selected FETs.
Since the FET is a depletion mode transistor, it is
usually necessary to drive its gate negative with
respect to ground to obtain the required drain
current. To provide this capability powered from a
single positive supply, the device includes a low
current negative supply generator. This generator
uses an internal oscillator and two external
capacitors, C
NB
and C
SUB
.
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ISSUE 1 - AUGUST 2001
4
ZNBG2000
ZNBG2001
TYPICAL APPLICATION CIRCUIT
APPLICATIONS
16k
INFORMATION
The above is a partial application circuit for the ZNBG
series showing all external components required for
appropriate biasing. The bias circuits are
unconditionally stable over the full temperature
range with the associated FETs and gate and drain
capacitors in circuit.
Capacitors C
D
and C
G
ensure that residual power
supply and substrate generator noise is not allowed
to affect other external circuits which may be
sensitive to RF interference. They also serve to
suppress any potential RF feedthrough between
stages via the ZNBG device. These capacitors are
required for all stages used. Values of 10nF and 4.7nF
respectively are recommended however this is
design dependent and any value between 1nF and
100nF could be used.
The capacitors C
NB
and C
SUB
are an integral part of
the ZNBGs negative supply generator. The negative
bias voltage is generated on-chip using an internal
oscillator. The required value of capacitors C
NB
and
C
SUB
is 47nF. This generator produces a low current
supply of approximately -3 volts. Although this
generator is intended purely to bias the external
FETs, it can be used to power other external circuits
via the C
SUB
pin.
Resistor R
CAL1
sets the drain current at which all
external FETs are operated. If any bias control circuit
is not required, its related drain and gate connections
may be left open circuit without affecting the
operation of the remaining bias circuits. If all FETs
associated with a current setting resistor are omitted,
the particular R
CAL
should still be included. The
supply current can be reduced, if required, by using a
high value R
CAL
resistor (e.g. 470k).
The ZNBG devices have been designed to protect the
external FETs from adverse operating conditions.
With a JFET connected to any bias circuit, the gate
output voltage of the bias circuit can not exceed the
range -3.5V to 0.7V, under any conditions including
powerup and powerdown transients. Should the
negative bias generator be shorted or overloaded so
that the drain current of the external FETs can no
longer be controlled, the drain supply to FETs is shut
down to avoid damage to the FETs by excessive
drain current.
The following diagram show the ZNBG2000/1 in
typical LNB applications.
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ISSUE 1 - AUGUST 2001
5
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