FemtoClocks™ Crystal-TO-LVDS
Frequency Synthesizer
844003-01
DATA SHEET
General Description
The 844003-01 is a 3 differential output LVDS Synthesizer
designed to generate Ethernet refer- ence clock frequencies.
Using a 19.53125MHz or 25MHz, 18pF parallel resonant crystal,
the following frequencies can be generated based on the settings
of 4 frequency select pins (DIV_SELA[1:0], DIV_SELB[1:0]):
625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003-01
has 2 output banks, Bank A with 1 differential LVDS output pair
and Bank B with 2 differential LVDS output pairs.
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above.
The 844003-01 uses IDT’s 3
rd
generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Ethernet jitter requirements. The 844003-01 is
packaged in a small 24-pin TSSOP package.
Features
•
•
•
•
•
•
•
•
Three differential LVDS output pairs on two banks, Bank A with
one LVDS pair and Bank B with two LVDS output pairs
Using a 19.53125MHz or 25MHz crystal, the two output banks
can be independently set for 625MHz, 312.5MHz, 156.25MHz
or 125MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 490MHz - 680MHz
RMS phase jitter @ 156.25MHz (1.875MHz – 20MHz):
0.56ps (typical)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
844003-01
Block Diagram
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
844003-01 Rev A 06/10/15
1
©2015 Integrated Device Technology, Inc.
844003-01 DATA SHEET
Table 1. Pin Descriptions
Number
1,
24
Name
DIV_SELB0,
DIV_SELB1
Input
Type
Pullup
Description
Division select pin for Bank B. Default = HIGH.
LVCMOS/LVTTL interface levels. See Table 3B.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Has an
internal pulldown resistor so the power-up default state of outputs and dividers
are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH, the
output pairs on Bank B are enabled. When logic LOW, the output pairs are in a
high impedance state. Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3E.
Output enable Bank A. Active High output enable. When logic HIGH, the output
pair in Bank A is enabled. When logic LOW, the output pair is in a high
impedance state. Has an internal pullup resistor so the default power-up state of
output is enabled. LVCMOS/LVTTL interface levels. See Table 3D.
Feedback divide select. When Low (default), the feedback divider is set for ÷25.
When HIGH, the feedback divider is set for ÷32. See Table 3C.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pullup
Division select pin for Bank A. Default = HIGH. See Table 3A.
LVCMOS/LVTTL interface levels.
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit
with a single-ended reference clock.
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to
low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended REF_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pin for Bank B outputs.
2
VCO_SEL
Input
Pullup
3
MR
Input
Pulldown
4
5, 6
V
DDO_A
QA0, nQA0
Power
Output
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12,
13
14
15,
16
FB_DIV
V
DDA
V
DD
DIV_SELA0,
DIV_SELA1
GND
XTAL_OUT,
XTAL_IN
Input
Power
Power
Input
Power
Input
Pulldown
17
REF_CLK
Input
18
19, 20
21, 22
23
XTAL_SEL
nQB1, QB1
nQB0, QB0
V
DDO_B
Input
Output
Output
Power
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
2
Rev A 06/10/15
MCU
京公网安备 11010802033920号
EEWORLD
