ICS843004I-04
F
EMTO
C
LOCKS
™ C
RYSTAL
/LVCMOS-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843004I-04 is a 4 output LVPECL Synthesizer
optimized to generate clock frequencies for a variety of
high performance applications. This device can select its
input reference clock from either a crystal input or a
single-ended clock signal. It can be configured to
generate 4 outputs with individually selectable divide-
by-one or divide-by-four function via the 4 frequency
select pins (F_SEL[3:0]). The ICS843004I-04 uses IDT’s
3
rd
generation low phase noise VCO technology and
can achieve 1ps or lower typical rms phase jitter. This
ensures that it will easily meet clocking requirements
for SDH (STM-1/STM-4/STM-16) and SONET (OC-3/
OC12/OC-48). This device is suitable for multi-rate and
multiple port line card applications. The ICS843004I-04
is conveniently packaged in a small 24-pin TSSOP
package.
F
EATURES
• Four LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.82ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.57ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.94ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
XTAL_IN
P
IN
A
SSIGNMENT
÷1
Phase
Detector
VCO
÷4
0
1
OSC
XTAL_OUT
CLK
Pulldown
INPUT_SEL
Pulldown
0
Q0
nQ0
1
M = ÷32
MR
Pulldown
F_SEL0
Pullup
0
1
Q1
nQ1
nQ1
Q1
V
CC
o
Q0
nQ0
MR
F_SEL3
nc
V
CCA
F_SEL0
V
CC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
F_SEL2
INPUT_SEL
CLK
V
EE
XTAL_IN
XTAL_OUT
F_SEL1
Pullup
0
1
ICS843004I-04
Q2
nQ2
F_SEL2
Pullup
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
0
1
Q3
nQ3
F_SEL3
Pullup
843004AGI-04
www.idt.com
1
REV. A JULY 26, 2010
ICS843004I-04
F
EMTO
C
LOCKS
™ C
RYSTAL
/LVCMOS-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
7,
10 ,
12,
18
8
9
11
13, 14
15, 19
16
17
20, 21
23, 24
Name
nQ1, Q1
V
CCO
Q0, nQ0
MR
F_SEL3,
F_SEL0,
F_SEL1,
F_SEL2
nc
V
CCA
V
CC
XTAL_OUT,
XTAL_IN
V
EE
CLK
INPUT_SEL
nQ3, Q3
Q2, nQ2
Type
Output
Power
Ouput
Input
Description
Differential output pair. LVPECL interface levels.
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Pullup
Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3.
No connect.
Analog supply pin.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Negative supply pins.
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or CLK inputs as the the PLL Reference source.
Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Input
Unused
Power
Power
Input
Power
Input
Input
Output
Output
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. O
UTPUT
C
ONFIGURATION
Inputs
F_SELx
0
1
0
1
0
1
0
1
XTAL (MHz)
19.44
19.44
18.75
18.75
19.53125
19.53125
20.141601
20.141601
AND
F
REQUENCY
R
ANGE
F
UNCTION
T
ABLE
Divider Value
÷1
÷4
÷1
÷4
÷1
÷4
÷1
÷4
Output Frequency (MHz)
Q0/nQ0:Q3/nQ3
622.08
155.52
600
150
625
156.25
644.5312
161.13
Application
SONET/SDH
SATA
10 Gigabit Ethernet
10 Gigabit Ethernet
66B/64B FEC
VCO
(MHz)
622.08
622.08
600
600
625
625
644.5312
644.5312
843004AGI-04
www.idt.com
2
REV. A JULY 26, 2010
ICS843004I-04
F
EMTO
C
LOCKS
™ C
RYSTAL
/LVCMOS-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
70°C/W (0 mps)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
120
10
120
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
CLK,
MR, INPUT_SEL
F_SEL0:F_SEL3
I
IL
Input Low Current
CLK,
MR, INPUT_SEL
F_SEL0:F_SEL3
V
CC
= V
IN
= 3.465
V
CC
= V
IN
= 3.465
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
843004AGI-04
www.idt.com
3
REV. A JULY 26, 2010
ICS843004I-04
F
EMTO
C
LOCKS
™ C
RYSTAL
/LVCMOS-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
17.5
Test Conditions
Minimum
Typical
Maximum
21.25
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 2, 3
155.52MHz,
Integration Range: 12kHz - 20MHz
156.25MHz,
Integration Range: 1.875MHz - 20MHz
622.08MHz,
Integration Range: 12kHz - 20MHz
20% to 80%
0.94
0.57
82
175
675
52
60
Test Conditions
Output Divider = ÷1
Output Divider = ÷4
Minimum
560
140
Typical
Maximum
680
170
75
Units
MHz
MHz
ps
ps
ps
ps
ps
%
%
t
sk(o)
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 4
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
Output Divider = ÷4
48
Output Divider = ÷1
40
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
CCO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Output skew measurements taken with all outputs in the same divide configuration.
NOTE 4: Please refer to the Phase Noise Plot.
843004AGI-04
www.idt.com
4
REV. A JULY 26, 2010
ICS843004I-04
F
EMTO
C
LOCKS
™ C
RYSTAL
/LVCMOS-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
V
CCA
= 2V
nQx
Qx
V
CC
,
V
CCO
Qx
SCOPE
nQy
Qy
tsk(o)
LVPECL
V
EE
nQx
-1.3V±0.165V
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Phase Noise Plot
O
UTPUT
S
KEW
Noise Power
Phase Noise Mask
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
f
1
Offset Frequency
f
2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS P
HASE
J
ITTER
O
UTPUT
R
ISE
/F
ALL
T
IME
nQ0:nQ3
Q0:Q3
t
PW
t
PERIOD
odc =
t
PW
t
PERIOD
x 100%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
843004AGI-04
www.idt.com
5
REV. A JULY 26, 2010
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