FemtoClock
®
Crystal-to-LVDS
Frequency Synthesizer
ICS844004I-104
DATA SHEET
General Description
The ICS844004I-104 is a 4 output LVDS Synthesizer optimized to
generate Fibre Channel reference clock frequencies. Using a
26.5625MHz 18pF parallel resonant crystal, the following
frequencies can be generated based on the two frequency select
pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz
and 53.125MHz. The ICS844004I-104 uses IDT’s 3
RD
generation low
phase noise VCO technology and can achieve <1ps typical rms
phase jitter, easily meeting Fibre Channel jitter requirements. The
ICS844004I-104 is packaged in a 32-pin VFQFN package.
Features
•
•
•
•
•
•
•
•
Four differential LVDS outputs
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
Supports the following output frequencies: 212.5MHz, 187.5MHz,
159.375MHz, 106.25MHz and 53.125MHz
VCO range: 560MHz - 680MHz
RMS phase jitter at 212.5MHz (637kHz – 10MHz), using a
26.5625MHz crystal: <1ps (typical)
Full 3.3V or 2.5V output supply modes
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Frequency Table
Inputs
Input
Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
23.4375
F_SEL1
F_SEL0
M
N
M/N
Output
Divider Divider Divider Frequency
Value
Value
Value
(MHz)
24
24
24
24
24
3
4
6
12
3
8
6
4
2
8
212.5
(default)
159.375
106.25
53.125
187.5
(default)
Pin Assignment
V
DDO
nQ1
32 31 30 29 28 27 26 25
Q0
nQ0
MR
nPLL_SEL
nc
nc
nc
nc
1
2
3
4
5
6
7
8
9
V
DDA
V
DDO
nQ2
Q1
nc
nc
Q2
24
Q3
nQ3
GND
nc
nc
nXTAL_SEL
REF_CLK
GND
0
0
1
1
0
0
1
0
1
0
ICS844004I-104
32 Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
10 11 12 13 14 15 16
XTAL_IN
F_SEL0
F_SEL1
V
DD
XTAL_OUT
nc
nc
23
22
21
20
19
18
17
Block Diagram
F_SEL[1:0]
nPLL_SEL
Pulldown
Pulldown
2
Q0
REF_CLK
Pulldown
26.5625MHz
1
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
nQ0
Q1
nQ1
Q2
nQ2
0
M = 24 (fixed)
Q3
nQ3
MR
Pulldown
ICS844004AKI-104 REVISION A DECEMBER 15, 2010
1
©2010 Integrated Device Technology, Inc.
ICS844004I-104 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 2
Name
Q0, nQ0
Output
Type
Description
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown
Frequency select pin. LVCMOS/LVTTL interface levels.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Power supply ground.
Pulldown
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between crystal or REF_CLK inputs as the PLL Reference source. Selects
XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL
interface levels.
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
3
MR
Input
Pulldown
4
5, 6, 7, 8, 15,
16, 20, 21,
28, 29
9
10,
12
11
13,
14
17, 22
18
19
23, 24
25, 32
26, 27
30, 31
nPLL_SEL
Input
Pulldown
nc
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT
XTAL_IN
GND
REF_CLK
nXTAL_SEL
nQ3, Q3
V
DDO
Q2, nQ2
nQ1, Q1
Unused
Power
Input
Power
Input
Power
Input
Input
Output
Power
Output
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Ω
ICS844004AKI-104 REVISION A DECEMBER 15, 2010
2
©2010 Integrated Device Technology, Inc.
ICS844004I-104 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
42.4°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.12
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
105
12
120
Units
V
V
V
mA
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.10
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
100
10
100
Units
V
V
V
mA
mA
mA
ICS844004AKI-104 REVISION A DECEMBER 15, 2010
3
©2010 Integrated Device Technology, Inc.
ICS844004I-104 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 3C. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
REF_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
REF_CLK,
MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
V
DD
= 3.3V
V
DD
= 2.5V
Input
High Current
Input
Low Current
V
DD
= V
IN
= 3.465V
or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
µA
Units
V
V
V
V
IL
I
IH
I
IL
-5
µA
Table 3D. LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.2
1.425
Test Conditions
Minimum
300
Typical
450
Maximum
600
50
1.65
50
Units
mV
mV
V
mV
Table 3E. LVDS DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.0
1.2
Test Conditions
Minimum
250
Typical
400
Maximum
550
50
1.4
50
Units
mV
mV
V
mV
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
23.33
Test Conditions
Minimum
Typical
Fundamental
26.5625
28.33
50
7
MHz
Maximum
Units
Ω
pF
ICS844004AKI-104 REVISION A DECEMBER 15, 2010
4
©2010 Integrated Device Technology, Inc.
ICS844004I-104 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew; NOTE 1, 2
212.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 3
106.25MHz, (637kHz -10MHz)
53.125MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0]
≠
÷3
F_SEL[1:0] = ÷3
250
48
40
0.73
0.78
0.92
0.95
0.75
500
52
60
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.66
170
113.33
56.66
35
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
Table 5B. AC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
tsk(o)
Output Skew; NOTE 1, 2
212.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 3
106.25MHz, (637kHz -10MHz)
53.125MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0]
≠
÷3
F_SEL[1:0] = ÷3
250
48
40
0.72
0.88
0.89
0.96
0.74
550
52
60
Minimum
186.67
140
93.33
46.67
Typical
Maximum
226.66
170
113.33
56.66
35
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
ICS844004AKI-104 REVISION A DECEMBER 15, 2010
5
©2010 Integrated Device Technology, Inc.
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