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Intel 860 Chipset: 82860
Memory Controller Hub (MCH)
Datasheet
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May 2001
Document Number:
290713-001
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
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intended for use in medical, life saving, or life sustaining applications.
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 82860 Memory Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel.
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Implementations of the I C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
®
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling
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*Other names and brands may be claimed as the property of others.
©
Copyright 2001, Intel Corporation
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Intel 82860 MCH Datasheet
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Contents
1
Introduction ........................................................................................................................13
1.1
1.2
1.3
1.4
Terminology ..........................................................................................................13
Reference Documents ..........................................................................................15
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Intel 860 Chipset System Architecture ................................................................16
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Intel 82860 MCH Overview .................................................................................18
1.4.1
Processor Interface ...............................................................................19
1.4.2
Memory Interface ..................................................................................20
1.4.3
AGP Interface........................................................................................22
1.4.4
Hub Interface_A ....................................................................................22
1.4.5
Hub Interface_B and Hub Interface_C ..................................................23
1.4.6
MCH Clocking .......................................................................................23
1.4.7
System Interrupts ..................................................................................24
1.4.8
Powerdown Flow ...................................................................................24
Host Interface Signals...........................................................................................27
Rambus* Channel A .............................................................................................30
Rambus* Channel B .............................................................................................31
Hub Interface_A Signals .......................................................................................32
Hub Interface_B ....................................................................................................32
Hub Interface_C....................................................................................................32
AGP Interface Signals...........................................................................................33
2.7.1
AGP Addressing Signals .......................................................................33
2.7.2
AGP Flow Control Signals .....................................................................34
2.7.3
AGP Status Signals ...............................................................................34
2.7.4
AGP Strobes .........................................................................................35
2.7.5
AGP/PCI Signals-Semantics .................................................................36
Clocks, Reset, and Miscellaneous ........................................................................39
Voltage References, PLL Power...........................................................................40
Strap Signals.........................................................................................................41
Pin States during Reset ........................................................................................41
2
Signal Description..............................................................................................................25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
Register Description ..........................................................................................................45
3.1
3.2
3.3
Register Terminology............................................................................................45
PCI Configuration Space Access..........................................................................46
I/O Mapped Registers ...........................................................................................49
3.3.1
CONF_ADDR—Configuration Address Register ..................................49
3.3.2
CONF_DATA—Configuration Data Register.........................................50
Host-Hub Interface_A Bridge Device Registers (Device 0) .................................51
3.4.1
VID—Vendor Identification Register (Device 0) ....................................53
3.4.2
DID—Device Identification Register (Device 0).....................................53
3.4.3
PCICMD—PCI Command Register (Device 0) .....................................54
3.4.4
PCISTS—PCI Status Register (Device 0).............................................55
3.4.5
RID—Revision Identification Register (Device 0)..................................56
3.4
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3.5
SUBC—Sub-Class Code Register (Device 0).......................................56
BCC—Base Class Code Register (Device 0)........................................56
MLT—Master Latency Timer Register (Device 0) .................................57
HDR—Header Type Register (Device 0) ..............................................57
APBASE—Aperture Base Configuration Register (Device 0) ...............57
SVID—Subsystem Vendor ID Register (Device 0)................................58
SID—Subsystem ID Register (Device 0)...............................................59
CAPPTR—Capabilities Pointer Register (Device 0) .............................59
GAR[0:15]—RDRAM* Device Group Architecture Register (Device 0) 60
MCHCFG—MCH Configuration Register (Device 0).............................61
FDHC—Fixed DRAM Hole Control Register (Device 0)........................63
PAM[0:6]—Programmable Attribute Map Registers (Device 0) ...........63
GBA[0:15]—RDRAM* Device Group Boundary Address Register
(Device 0) ..............................................................................................67
3.4.19 RDPS—RDRAM* Device Pool Sizing Register (Device 0)....................68
3.4.20 DRD—RDRAM* Device Register Data Register (Device 0)..................69
3.4.21 RICM—RDRAM* Device Initialization Control Management Register
(Device 0) ..............................................................................................69
3.4.22 SMRAM—System Management RAM Control Register (Device 0) .....71
3.4.23 ESMRAMC—Extended System Management RAM Control Register
(Device 0) ..............................................................................................72
3.4.24 ACAPID—AGP Capability Identifier Register (Device 0).......................73
3.4.25 AGPSTAT—AGP Status Register (Device 0) .......................................74
3.4.26 AGPCMD—AGP Command Register (Device 0)..................................75
3.4.27 AGPCTRL – AGP Control Register.......................................................76
3.4.28 APSIZE—Aperture Size (Device 0) .......................................................76
3.4.29 ATTBASE—Aperture Translation Table Base Register (Device 0)......77
3.4.30 AMTT—AGP Interface Multi-Transaction Timer Register (Device 0) ...77
3.4.31 LPTT—Low Priority Transaction Timer Register (Device 0) .................78
3.4.32 RDTR—RDRAM* Device Timing Register (Device 0) ..........................79
3.4.33 TOM—Top of Low Memory Register (Device 0) ...................................80
3.4.34 ERRSTS—Error Status Register (Device 0) .........................................81
3.4.35 ERRCMD—Error Command Register (Device 0) .................................83
3.4.36 SMICMD—SMI Command Register (Device 0) ....................................85
3.4.37 SCICMD—SCI Command Register (Device 0) .....................................86
3.4.38 DRAMRC—RDRAM* Device Refresh Control Register (Device 0) ......86
3.4.39 SKPD—Scratchpad Data (Device 0).....................................................88
3.4.40 DERRCTL_STS—DRAM Error Control/Status Register (Device 0) ....88
3.4.41 EAP—Error Address Pointer Register (Device 0) .................................89
3.4.42 MISC_CNTL—Miscellaneous Control Register (Device 0) ...................89
AGP Bridge Registers (Device 1) .........................................................................90
3.5.1
VID1—Vendor Identification Register (Device 1) ..................................91
3.5.2
DID1—Device Identification Register (Device 1)...................................91
3.5.3
PCICMD1—PCI-PCI Command Register (Device 1)............................92
3.5.4
PCISTS1—PCI-PCI Status Register (Device 1)....................................93
3.5.5
RID1—Revision Identification Register (Device 1)................................94
3.5.6
SUBC1—Sub-Class Code Register (Device 1).....................................94
3.5.7
BCC1—Base Class Code Register (Device 1)......................................94
3.5.8
MLT1—Master Latency Timer Register (Device 1) ...............................95
3.5.9
HDR1—Header Type Register (Device 1) ............................................95
3.5.10 PBUSN1—Primary Bus Number Register (Device 1) ...........................95
3.5.11 SBUSN1—Secondary Bus Number Register (Device 1) ......................96
3.5.12 SUBUSN1—Subordinate Bus Number Register (Device 1)..................96
3.5.13 SMLT1—Secondary Master Latency Timer Register (Device 1) .........97
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.4.12
3.4.13
3.4.14
3.4.15
3.4.16
3.4.17
3.4.18
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3.6
3.7
IOBASE1—I/O Base Address Register (Device 1) ...............................98
IOLIMIT1—I/O Limit Address Register (Device 1) ................................98
SSTS1—Secondary PCI-PCI Status Register (Device 1) .....................99
MBASE1—Memory Base Address Register (Device 1) ......................100
MLIMIT1—Memory Limit Address Register (Device 1) .......................101
PMBASE1—Prefetchable Memory Base Address Register
(Device 1) ............................................................................................102
3.5.20 PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)103
3.5.21 BCTRL1—PCI-PCI Bridge Control Register (Device 1) ......................104
3.5.22 ERRCMD1—Error Command Register (Device 1) .............................105
Hub Interface_B Bridge Registers (Device 2) .....................................................106
3.6.1
VID2—Vendor Identification Register (Device 2) ................................107
3.6.2
DID2—Device Identification Register (Device 2).................................107
3.6.3
PCICMD2—PCI-PCI Command Register (Device 2)..........................108
3.6.4
PCISTS2—PCI-PCI Status Register (Device 2)..................................109
3.6.5
RID2—Revision Identification Register (Device 2)..............................110
3.6.6
SUBC2—Sub-Class Code Register (Device 2)...................................110
3.6.7
BCC2—Base Class Code Register (Device 2)....................................110
3.6.8
MLT2—Master Latency Timer Register (Device 2) .............................111
3.6.9
HDR2—Header Type Register (Device 2) ..........................................111
3.6.10 PBUSN2—Primary Bus Number Register (Device 2) .........................111
3.6.11 SBUSN2—Secondary Bus Number Register (Device 2) ....................112
3.6.12 SUBUSN2—Subordinate Bus Number Register (Device 2)................112
3.6.13 SMLT2—Secondary Master Latency Timer Register (Device 2) .......112
3.6.14 IOBASE2—I/O Base Address Register (Device 2) .............................113
3.6.15 IOLIMIT2—I/O Limit Address Register (Device 2) ..............................113
3.6.16 SSTS2—Secondary PCI-PCI Status Register (Device 2) ...................114
3.6.17 MBASE2—Memory Base Address Register (Device 2) ......................115
3.6.18 MLIMIT2—Memory Limit Address Register (Device 2) .......................116
3.6.19 PMBASE2—Prefetchable Memory Base Address Register
(Device 2) ............................................................................................117
3.6.20 PMLIMIT2—Prefetchable Memory Limit Address Register (Device 2)118
3.6.21 BCTRL2—PCI-PCI Bridge Control Register (Device 2) ......................119
3.6.22 ERRCMD2—Error Command Register (Device 2) .............................121
Hub Interface_C Bridge Registers (Device 3).....................................................122
3.7.1
VID3—Vendor Identification Register (Device 3) ................................123
3.7.2
DID3—Device Identification Register (Device 3).................................123
3.7.3
PCICMD3—PCI-PCI Command Register (Device 3)..........................124
3.7.4
PCISTS3—PCI-PCI Status Register (Device 3)..................................125
3.7.5
RID3—Revision Identification Register (Device 3)..............................126
3.7.6
SUBC3—Sub-Class Code Register (Device 3)...................................126
3.7.7
BCC3—Base Class Code Register (Device 3)....................................126
3.7.8
MLT3—Master Latency Timer Register (Device 3) .............................127
3.7.9
HDR3—Header Type Register (Device 3) ..........................................127
3.7.10 PBUSN3—Primary Bus Number Register (Device 3) .........................127
3.7.11 SBUSN3—Secondary Bus Number Register (Device 3) ....................128
3.7.12 SUBUSN3—Subordinate Bus Number Register (Device 3)................128
3.7.13 SMLT3—Secondary Master Latency Timer Register (Device 3) .......128
3.7.14 IOBASE3—I/O Base Address Register (Device 3) .............................129
3.7.15 IOLIMIT3—I/O Limit Address Register (Device 3) ..............................129
3.7.16 SSTS3—Secondary PCI-PCI Status Register (Device 3) ...................130
3.7.17 MBASE3—Memory Base Address Register (Device 3) ......................131
3.7.18 MLIMIT3—Memory Limit Address Register (Device 3) .......................132
3.5.14
3.5.15
3.5.16
3.5.17
3.5.18
3.5.19
Intel 82860 MCH Datasheet
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