FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ICS843001-21
Description
The ICS843001-21 is a a highly versatile, low
phase noise LVPECL Synthesizer which can
HiPerClockS™
generate low jitter reference clocks for a variety of
communications applications and is a member of
the HiPerClocks
TM
family of high performance clock
solutions from IDT. The dual crystal interface allows the
synthesizer to support up to two communications standards in a
given application (i.e. 1GB Ethernet with a 25MHz crystal and 1Gb
Fibre Channel using a 26.5625MHz crystal). The rms phase jitter
performance is typically less than 1ps, thus making the device
acceptable for use in demanding applications such as OC48
SONET and 10Gb Ethernet. The ICS843001-21 is packaged in a
small 24-pin TSSOP package.
Features
•
•
•
•
•
•
One 3.3Vdifferential LVPECL output pair and
one LVCMOS/LVTTL single-ended reference clock output
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
VCO range: 560MHz – 700MHz
Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
Selectable ÷1 or ÷2 operation
RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.80ps (typical)
Offset
Noise Power
100Hz ................ -60.3 dBc/Hz
1kHz .................. -88.5 dBc/Hz
10kHz ................ -111.9 dBc/Hz
100kHz .............. -113.0 dBc/Hz
ICS
•
•
•
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
3
N2:N0
SEL0
Pulldown
SEL1
Pulldown
N
XTAL_IN0
000
001
010
011
100
101
110
111
÷1
÷2
÷3
÷4
(default)
÷5
÷6
÷8
÷10
V
CCO_CMOS
N0
N1
N2
V
CCO_PECL
Q0
Q0
V
EE
V
CCA
V
CC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REF_CLK
V
EE
OE_REF
M2
M1
M0
MR
SEL1
SEL0
TEST_CLK
XTAL_IN0
XTAL_OUT0
OSC
XTAL_OUT0
XTAL_IN1
00
11
Q0
OSC
XTAL_OUT1
TEST_CLK
Pulldown
01
Phase
Detector
VCO
10
01
00
ICS843001-21
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
Q0
10
000
001
010
011
100
101
M
÷18
÷22
÷24
÷25
÷32
(default)
÷40
MR
Pulldown
M2:M0
3
REF_CLK
OE_REF
Pulldown
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
1
ICS843001AG-21 REV. AMARCH 15, 2007
ICS843001-21
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1
2, 3
4
5
6, 7
8, 23
9
10
11,
12
13,
14
15
16, 17
Name
V
CCO_CMOS
N0, N1
N2
V
CCO_PECL
Q0, Q0
V
EE
V
CCA
V
CC
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
TEST_CLK
SEL0, SEL1
Power
Input
Input
Power
Output
Power
Power
Power
Input
Input
Input
Input
Pulldown
Pulldownp
Pullup
Pulldown
Type
Description
Output supply pin for REF_CLK output.
Output divider select pins. Default ÷4. LVCMOS/LVTTL interface levels.
See Table 3C.
Output supply pin for LVPECL output.
Differential output pair. LVPECL interface levels.
Negative supply pins.
Analog supply pin.
Core supply pin.
Parallel resonant crystal interface.
XTAL_OUT1 is the output, XTAL_IN1 is the input.
Parallel resonant crystal interface.
XTAL_OUT0 is the output, XTAL_IN0 is the input.
LVCMOS/LVTTL clock input.
Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true output Q0 to go low and the inverted output Q0 to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Feedback divider select pins. Default ÷32. See Table 3B
LVCMOS/LVTTL interface levels.
Reference clock output enable. Default Low. LVCMOS/LVTTL interface levels.
Reference clock output. LVCMOS/LVTTL interface levels.
18
MR
Input
Pulldown
19, 20
21
22
24
M0, M1
M2
OE_REF
REF_CLK
Input
Input
Input
Output
Pulldown
Pullup
Pulldown
NOTE:
Pullup and Pulldown
refer to intenal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
7
Maximum
Units
pF
k
Ω
k
Ω
Ω
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
2
ICS843001AG-21 REV. AMARCH 15, 2007
ICS843001-21
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Common Configuration Table
Input
Reference Clock (MHz)
27
24.75
14.8351649
19.44
19.44
19.44
19.44
19.53125
25
25
25
25
25
26.5625
26.5625
26.5625
31.25
M Divider
Value
22
24
40
32
32
32
32
32
25
25
24
24
24
24
24
24
18
N Divider
Value
8
8
8
4
8
1
2
4
5
10
6
4
8
6
3
4
5
Output Frequency
(MHz)
74.25
74.25
74.1758245
155.52
77.76
622.08
311.04
156.25
125
62.5
100
150
75
106.25
212.5
159.375
187.5
VCO (MHz)
594
594
593.4066
622.08
622.08
622.08
622.08
625
625
625
600
600
600
637.5
637.5
637.5
562.5
Application
HDTV
HDTV
HDTV
SONET
SONET
SONET
SONET
10 GigE
1 GigE
1 GigE
PCI Express
SATA
SATA
Fibre Channel 1
4 Gig Fibre Channel
10 Gig Fibre Channel
12 GigE
Table 3B. Programmable M Output Divider Function Table
Inputs
M2
0
0
0
0
1
1
M1
0
0
1
1
0
0
M0
0
1
0
1
0
1
M Divider
Value
18
22
24
25
32
40
Input Frequency (MHz)
Minimum
31.1
25.5
23.3
22.4
17.5
14.0
Maximum
38.9
31.8
29.2
28.0
21.9
17.5
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
3
ICS843001AG-21 REV. AMARCH 15, 2007
ICS843001-21
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 3C. Programmable N Output Divider
Function Table
Inputs
N2
0
0
0
0
1
1
1
1
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
M Divider
Value
1
2
3
4
5
6
8
10
Table 3D. Bypass Mode Function Table
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Reference
XTAL0
XTAL1
TEST_CLK
TEST_CLK1
PLL Mode
1
2
8
10
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
4
ICS843001AG-21 REV. AMARCH 15, 2007
ICS843001-21
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characterisitcs
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, V
O
(LVCMOS)
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-0.5V to V
CCO_CMOS
+ 0.5V
70°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCA
= V
CCO_CMOS
= V
CCO_PECL
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
170
11
8
Units
V
V
V
mA
mA
mA
V
CCO_PECL,
Output Supply Voltage
V
CCO_CMOS
I
EE
I
CCA
I
CCO_PECL,
I
CCO_CMOS
Power Supply Current
Analog Supply Current
Output Supply Current
IDT™ / ICS™
LVPECL FREQUENCY SYNTHESIZER
5
ICS843001AG-21 REV. AMARCH 15, 2007
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