Crystal-to-LVPECL 133MHz Clock
Synthesizer
843S104I-133
Data Sheet
General Description
The 843S104I-133 is a PLL-based clock synthesizer specifically
designed for low phase noise applications. This device generates a
133.33MHz differential LVPECL clock from an input reference of
25MHz. The input reference may be derived from an external source
or by the addition of a 25MHz crystal to the on-chip crystal oscillator.
An external reference is applied to the PCLK, nPCLK pins.The
device offers spread spectrum clock output for reduced EMI
applications. An I
2
C bus interface is used to enable or disable spread
spectrum operation as well as to select either a down spread value of
-0.35% or -0.5%.The 843S104I-133 is available in a lead-free
32-Lead VFQFN package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Four LVPECL output pairs
Crystal oscillator interface: 25MHz
Differential PCLK, nPCLK input pair
PCLK, nPCLK supports the following input types: LVPECL, CML,
SSTL
Output frequency: 133.33MHz
PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
RMS phase jitter @ 133.33MHz (12kHz – 20MHz):
1.2ps (typical)
I
2
C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) package
Block Diagram
REF_SEL
Pulldown
PCLK
Pulldown
nPCLK
Pullup/Pulldown
25MHz
Pin Assignment
nQ1
nQ2
V
CC
V
CC
Q1
V
CC
V
EE
Q2
1
4
32 31 30 29 28 27 26 25
Q[1:4]
nQ[1:4]
V
CC
REF_SEL
1
2
24
V
EE
PLL
OSC
0
4
XTAL_IN
23 nQ3
22
21
Q3
V
CC
V
EE
3
PCLK 4
nPCLK
5
6
XTAL_OUT
20 V
EE
19 nQ4
18
17
9
V
EE
SDATA
Pullup
V
EE
I
2
C
SCLK
Pullup
V
CCA
7
V
EE
8
10 11 12 13 14 15 16
XTAL_IN
V
CC_XOSC
XTAL_OUT
SDATA
SCLK
V
EE
nc
Q4
V
CC
Logic
843S104I-133
32-Lead VFQFN
5.0mm x 5.0mm package body
© Integrated Device Technology, Inc
1
Revision B April 28, 2016
843S104I-133 Data Sheet
Table 1. Pin Descriptions
Number
1, 17, 21, 25,
28, 29
2
3, 6, 8, 9,
10, 20, 24, 32
4
5
7
11
12,
13
14
15
16
18,19
22, 23
26, 27
30, 31
Name
V
CC
REF_SEL
V
EE
PCLK
nPCLK
V
CCA
V
CC_XOSC
XTAL_IN,
XTAL_OUT
nc
SCLK
SDATA
Q4, nQ4
Q3, nQ3
Q2, nQ2
Q1, nQ1
Power
Input
Power
Input
Input
Power
Power
Input
Unused
Input
I/O
Output
Output
Output
Output
Pullup
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Core supply pins.
Select input for XTAL (LOW) or REF_IN (HIGH).
LVCMOS/LVTTL interface levels.
Negative power supply pins.
Non-inverting external 25MHz differential reference input.
LVPECL input levels.
Inverting external 25MHz differential reference input. LVPECL input levels.
Analog supply for PLL.
Analog supply for crystal oscillator.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
No connect.
I
2
C compatible SCLK. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
I
2
C compatible SDATA. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
R
PULLDOWN
Input Pulldown Resistor
© Integrated Device Technology, Inc
2
Revision B April 28, 2016
843S104I-133 Data Sheet
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I
2
C serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock output
buffers, can be individually enabled or disabled. The registers
associated with the serial interface initialize to their default settings
upon power-up, and therefore, use of this interface is optional. Clock
device register changes are normally made upon system
initialization, if any are required.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block
write and block read operations from the controller. For block
write/read operations, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the ability to
stop after any complete byte has been transferred. For byte write and
byte read operations, the system controller can access individually
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 3A.
The block write and block read protocol is outlined in Table 3B, while
Table 3C outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit
Description
7
0 = Block read or block write operation,
1 = Byte read or byte write operation.
6, 5
Chip select address, set to
“00” to access device.
4:0
Byte offset for byte read or byte write
operation. For block read or block write
operations, these bits must be “00000”.
© Integrated Device Technology, Inc
3
Revision B April 28, 2016
843S104I-133 Data Sheet
Table 3B. Block Read and Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
Description = Block Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data byte 2 - 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
Description = Block Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
Stop
Table 3C. Byte Read and Byte Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29
Description = Byte Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Data byte - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Description = Byte Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data from slave - 8 bits
Not Acknowledge
Stop
Control Registers
© Integrated Device Technology, Inc
4
Revision B April 28, 2016
843S104I-133 Data Sheet
Table 3D. Byte 0: Control Register 0
Bit
7
6
@Power-up
0
1
Name
Reserved
Q4EN
Description
Reserved
Q4, nQ4 Output Enable
0 = Low
1 = Enable
Q3, nQ3 Output Enable
0 = Low1 = Enable
Q2, nQ2 Output Enable
0 = Low
1 = Enable
Q1, nQ1 Output Enable
0 = Low
1 = Enable
Reserved
Reserved
Reserved
Table 3G. Byte 3:Control Register 3
Bit
7
6
5
4
3
2
1
0
@Power-up
1
0
1
0
1
1
1
1
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
1
Q3EN
4
1
Q2EN
3
2
1
0
1
1
0
0
Q1EN
Reserved
Reserved
Reserved
Table 3H. Byte 4: Control Register 4
Bit
7
6
5
4
@Power-up
0
0
0
0
0
0
0
1
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3E. Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Power-up
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3
2
1
0
Table 3I. Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Power-up
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 3F. Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Power-up
1
1
1
0
1
0
1
0
Name
SS_SEL
Reserved
Reserved
Reserved
Reserved
SSM
Reserved
Reserved
Description
Spread Spectrum Selection
0 = -0.35%, 1 = - 0.5%
Reserved
Reserved
Reserved
Reserved
Q Spread Spectrum Enable
0 = Spread Off,
1 = Spread On
Reserved
Reserved
© Integrated Device Technology, Inc
5
Revision B April 28, 2016
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