D-110-0068 datasheet, PDF - EEWORLD Datasheet

D-110-0068: DescriptionD-110-0068; CategoryThe connector; File Size856KB，17 Pages; ManufacturerTE Connectivity; Websitehttp://www.te.com

Download Datasheet Parametric View All

D-110-0068 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	D-110-0068	-	-	View	Buy Now

D-110-0068

Parameter Name	Attribute value
Sealable	no
Connector type	Solder Sleeve Wire Terminator
sawtooth	no
Crimp barrel type	Closed crimping barrel
Insulated	Yes
Insulation Materials	Heat shrinkable radiation cross-linked modified polyvinylidene fluoride
Unit weight (g)	1
Insulating sleeve material	Polyvinyl fluoride
Terminal and connector types	Connector
Termination method	welding
with conductor insulation	Without
Wire Size (mm²)	.75 – .5
Wire insulation diameter (maximum)	1.4 mm [ .055 in ]
total length	6.1 mm [ .24 in ]
Inner diameter (restored)	1.27 mm [ .05 in ]
Outer diameter (mm)	2.794
fluid resistance	splash proof
Overload	no
Meet government qualifications	no
Encapsulation method	box
Package quantity	500
Pressing barrel color	Clear Blue

U VISION4 crack help: The tutorial says that when you crack to the last step, the time will be displayed in the white box, for example, 2020. My U VISION has been cracked to the last step, and there is no time displayed in...; NJMKL 51mcu

[Repost] We love technology as much as we love life - Los Angeles Windows Hardware Engineering Conference (serial): First photo: Our Festival As an avid hardware enthusiast, I started paying attention to the WinHEC conference in the United States when I was in high school. Today, I finally have the opportunity to a...; 副团长夫人 Talking

Help with understanding of FPGA generating FSK modulation signal: ( 5 ) Both channels can generate FSK modulation waves. The frequency of the internal modulation signal is no more than 10Hz , the upper side frequency is 12kHz , and the lower side frequency is 8kHz ;...; 523335234 FPGA/CPLD

Ultrasound ECG Medical Electronics Related Information Sharing: Study materials and papers, share with everyone. [[i] This post was last edited by smart_shan on 2013-9-2 09:25 [/i]]...; smart_shan Medical Electronics

Is the '*' symbol in Verilog considered a multiplier?: Does a '*' in a Verilog formula mean that a multiplier is used? If there is a '*' sign in the array, does it count as using a multiplier? The following statement: ref_line0_data[0*36+:36];...; 1nnocent FPGA/CPLD

【Qinheng RISC-V core CH582】Evaluation summary: According to the submitted evaluation plan: 1. Unboxing and hardware appreciation 2. Development environment construction and data collection and download 3. Official routine evaluation of the develop...; kit7828 Domestic Chip Exchange

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components