55/9952-24-6(LAT3) datasheet, PDF

55/9952-24-6(LAT3): Description55/9952-24-6(LAT3); CategoryWire/cable; File Size856KB，17 Pages; ManufacturerTE Connectivity; Websitehttp://www.te.com

Download Datasheet Parametric View All

55/9952-24-6(LAT3) Overview

55/9952-24-6(LAT3)

Parameter Name	Attribute value
Cable type	Specification 55/
Cable type	dedicated structure
Product Categories	High performance - Spec 44, 55 and RCW
Number of shares	19
Number of conductors	1
Rated voltage (V)	600
Resistance maximum value	106.2 Ω/1000 meters (at 20°C)
Insulation Materials	Radiation cross-linked modified fluoropolymer
conductor material	Silver-plated high-strength copper alloy, Silver-plated high-strength copper alloy
Wire color	blue
Weight (kg/km)	2.78
Wire size (AWG)	24
Wire size (mm²)	.2
Conductor diameter	.58 mm [ .0228 in ]
Overall outer diameter	.95 mm [ .0374 in ]
Conductor diameter range	.57 – .59 mm [ .022 – .023 in ]
Wire diameter	.95 mm [ .0374 in ]
Operating temperature range (°C)	-65 – 200
Wire source	U.K.

[TI recommended course] #TI LED driver# RGB LED circuit design reference: //training.eeworld.com.cn/TI/show/course/5651...; Orima TI Technology Forum

Mingdeyang FPGA Series Course Phase 1 Chapter 2 FPGA Design Process: [align=left][color=rgb(51, 51, 51)][font="][size=17px]FPGA design process is the process of developing FPGA chips using EDA development software and programming tools. The typical FPGA development pro...; guyu_1 FPGA/CPLD

Looking for a pl/m language editor: There is a project that must use pl/m source insight does not support pl/m is there any editor that can support pl/m, can it have syntax highlighting etc. Thanks...; xiaozhou Embedded System

Thermal relay tripped: There are 4 thermal relays at the lower end of a frequency converter. When the circuit breaker at the upper end of the frequency converter is closed under no-load conditions, some of the thermal relay...; eeleader Industrial Control Electronics

Need your help.: Hello everyone, I am working on a graduation project on an automatic music playing circuit based on hardware (FPGA), but I don’t know how to write the opening report. Please help me. There are several...; dangzhiyi FPGA/CPLD

The project needs to be exposed to Renesas chips: I was given a developed board to familiarize myself with and use an oscilloscope to test the IO, but there is no separate IO or interface on the board, but both require the driver of the previous chip...; #sudoroot Renesas Electronics MCUs

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components