571THAFREQDGR datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 571THAFREQDGR

571THAFREQDGR: DescriptionCMOS Output Clock Oscillator, 10MHz Min, 160MHz Max, ROHS COMPLIANT PACKAGE-8; CategoryPassive components oscillator; File Size316KB，26 Pages; ManufacturerSilicon Laboratories Inc

Download Datasheet Parametric View All

571THAFREQDGR Overview

CMOS Output Clock Oscillator, 10MHz Min, 160MHz Max, ROHS COMPLIANT PACKAGE-8

571THAFREQDGR Parametric

Parameter Name	Attribute value
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRISTATE; ENABLE/DISABLE FUNCTION; TAPE AND REEL
Maximum control voltage	2.5 V
Minimum control voltage
maximum descent time	1 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	145 ppm
frequency stability	20%
linearity	10%
Manufacturer's serial number	SI571
Installation features	SURFACE MOUNT
Maximum operating frequency	160 MHz
Minimum operating frequency	10 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	1 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Base Number Matches	1

Preview

Download Datasheet

View All

Si 5 7 0 / S i 5 7 1

R E L I M I N A R Y

A TA

H E E T

N Y

- R

A T E

C P

R O G R A M M A B L E

XO/VCXO

Features

Any-rate programmable output

frequencies from 10 to 945 MHz and

select frequencies to 1.4 GHz

C serial interface

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available LVPECL, CMOS,

LVDS, and CML outputs

Industry-standard 5x7 mm

package

Pb-free/RoHS-compliant

1.8, 2.5, or 3.3 V supply

Si5602

Applications

SONET / SDH

xDSL

10 GbE LAN / WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

Ordering Information:

See page 21.

Description

The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are

user-programmable to any output frequency from 10 to 945 MHz and select

frequencies to 1400 MHz with <1 ppb resolution. The device is programmed

via an I

C serial interface. Unlike traditional XO/VCXOs where a different

crystal is required for each output frequency, the Si57x uses one fixed-

frequency crystal and a DSPLL clock synthesis IC to provide any-rate

frequency operation. This IC-based approach allows the crystal resonator to

provide exceptional frequency stability and reliability. In addition, DSPLL

clock synthesis provides superior supply noise rejection, simplifying the task

of generating low-jitter clocks in noisy environments typically found in

communication systems.

Pin Assignments:

See page 20.

(Top View)

SDA

SCL

GND

CLK–

CLK+

Functional Block Diagram

CLK-

CLK+

Si570

SDA

Fixed

Frequency

Any-rate

10-1400 MHz

DSPLL Clock

Synthesis

SCL

SDA

GND

CLK–

CLK+

Si571 only

ADC

GND

Si571

Si570/Si571

Rev. 0.31 8/07

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Recommended Resources

One of the AC contactor low voltage starting circuits

STK4161II audio IC circuit diagram

DM680l/DM6801A/DM6801B type 3 1/2 digit digital thermometer circuit

Single-phase full-wave resistive load rectifier circuit

Y-△ starting circuit for non-energized switching of motors (1)

875p computer motherboard circuit diagram_088

Under CE, use the port to operate the GPS module, power consumption is related: In CE, use the Com port to operate GPS. If the GPS port is open, the GPS module is in operation and consumes more power. If the port is closed, the GPS module is in stop state and does not consume pow...; asdfgh123 Embedded System

Reprint of the 09.05 version of the Common Component Selection Table: Well, it is reproduced, the copyright belongs to the original author....; aiwenzx Analog electronics

How to draw PCB package according to component size? Do you need to add 3D when drawing the package yourself?: For example:I draw a 1.2mm*2mm block diagram, and then draw 0.2*0.4 pins. Is it enough to place them according to the pin spacing? What other steps are needed? Why does the picture I drew look wrong?...; pengbiao1210 PCB Design

Which two pins of STM32F103C8T6 should SCL and SDA of 4-port OLED be connected to?: As the title says, in the 4-interface OLED, which two pins of STM32F103C8T6 are connected to SCL and SDA? The OLED is a 0.96-inch 12864OLED. I have been searching for a long time but couldn't find it....; zhuuu stm32/stm8

Project subcontracting: INTOUCH software development (nearly one million): Real-time/historical database Database front-end tool Web publishing server Web publishing client InTouch development version software Dream Report Report tool Based on the above tools, develop. Trans...; 6565 Embedded System

Mo Xuyou-I'm leaving: The international situation is a bit tense recently, with THAAD entering South Korea, Japan making trouble, and the US conducting military exercises. This morning, I saw the message from the administr...; suoma Suggestions & Announcements

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components