3D7323Z-6 datasheet, PDF - EEWORLD Datasheet

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3D7323Z-6: DescriptionMONOLITHIC TRIPLE FIXED DELAY LINE; Categorylogic logic; File Size127KB，4 Pages; ManufacturerData Delay Devices; Environmental Compliance

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3D7323Z-6 Overview

MONOLITHIC TRIPLE FIXED DELAY LINE

3D7323Z-6 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SOIC
package instruction	0.150 INCH, ROHS COMPLIANT, SOIC-8
Contacts	8
Reach Compliance Code	compli
series	7323
Input frequency maximum value (fmax)	55.5 MHz
JESD-30 code	R-PDSO-G8
length	4.88 mm
Logic integrated circuit type	ACTIVE DELAY LINE
Number of functions	1
Number of taps/steps	3
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	5 mA
programmable delay line	NO
Prop。Delay @ Nom-Su	7 ns
Certification status	Not Qualified
Maximum seat height	1.82 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	6 ns
width	3.91 mm
Base Number Matches	1

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3D7323

MONOLITHIC TRIPLE

FIXED DELAY LINE

(SERIES 3D7323)

FEATURES

•

All-silicon, low-power CMOS technology

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

Low ground bounce noise

Leading- and trailing-edge accuracy

Delay range:

6 through 6000ns

Delay tolerance:

2% or 1.0ns

Temperature stability:

±3%

typ (-40C to 85C)

Vdd stability:

±1%

typical (4.75V to 5.25V)

Minimum input pulse width:

20% of total

delay

14-pin DIP available as drop-in replacement for

hybrid delay lines

GND

PACKAGES

VDD

N/C

GND

VDD

N/C

3D7323M DIP

3D7323H Gull-Wing

GND

VDD

3D7323Z SOIC

(150 Mil)

3D7323 DIP

3D7323G Gull-Wing

3D7323K Unused pins

removed

For mechanical dimensions, click

here

For package marking details, click

here

FUNCTIONAL DESCRIPTION

The 3D7323 Triple Delay Line product family consists of fixed-delay

CMOS integrated circuits. Each package contains three matched,

independent delay lines. Delay values can range from 6ns through

6000ns. The input is reproduced at the output without inversion,

shifted in time as per the user-specified dash number. The 3D7323

is TTL- and CMOS-compatible, capable of driving ten 74LS-type

loads, and features both rising- and falling-edge accuracy.

PIN DESCRIPTIONS

VDD

GND

N/C

Delay Line 1 Input

Delay Line 2 Input

Delay Line 3 Input

Delay Line 1 Output

Delay Line 2 Output

Delay Line 3 Output

+5 Volts

Ground

No Connection

The all-CMOS 3D7323 integrated circuit has been designed as a

reliable, economic alternative to hybrid TTL fixed delay lines. It is

offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

DIP-8

3D7323M

3D7323H

-6

-8

-10

-15

-20

-25

-30

-40

-50

-100

-200

-500

-1000

-6000

NOTE:

PART NUMBER

SOIC-8

DIP-14

3D7323Z

3D7323

3D7323G

-6

-8

-10

-15

-20

-25

-30

-40

-50

-100

-200

-500

-1000

-6000

DIP-14

3D7323K

-6

-8

-10

-15

-20

-25

-30

-40

-50

-100

-200

-500

-1000

-6000

DELAY

PER LINE

(ns)

1.0

100

2.0

200

4.0

500

10.0

1000

6000

±120

Max Operating

Frequency

55.5 MHz

41.6 MHz

33.3 MHz

22.2 MHz

16.7 MHz

13.3 MHz

11.1 MHz

8.33 MHz

6.67 MHz

3.33 MHz

1.67 MHz

0.67 MHz

0.33 MHz

0.05 MHz

INPUT RESTRICTIONS

Absolute Max

Min Operating

Oper. Freq.

Pulse Width

125.0 MHz

111.0 MHz

100.0 MHz

83.3 MHz

71.4 MHz

62.5 MHz

50.0 MHz

25.0 MHz

12.5 MHz

5.00 MHz

2.50 MHz

0.42 MHz

9.0 ns

12.0 ns

15.0 ns

22.5 ns

30.0 ns

37.5 ns

45.0 ns

60.0 ns

75.0 ns

150.0 ns

300.0 ns

750.0 ns

1500.0 ns

9000.0 ns

Absolute Min

Oper. P.W.

4.0 ns

4.5 ns

5.0 ns

6.0 ns

7.0 ns

8.0 ns

10.0 ns

20.0 ns

40.0 ns

100.0 ns

200.0 ns

1200.0 ns

Any delay between 10 and 6000 ns not shown is also available.

2006

Data Delay Devices

Doc #06015

5/10/2006

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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