3D7424-.75 datasheet, PDF - EEWORLD Datasheet

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3D7424-.75: DescriptionMONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE; Categorylogic logic; File Size164KB，6 Pages; ManufacturerData Delay Devices; Environmental Compliance

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3D7424-.75 Overview

MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

3D7424-.75 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Data Delay Devices
Parts packaging code	DIP
package instruction	ROHS COMPLIANT, DIP-14
Contacts	14
Reach Compliance Code	compli
series	7424
Input frequency maximum value (fmax)	19 MHz
JESD-30 code	R-PDIP-T14
length	19.305 mm
Logic integrated circuit type	ACTIVE DELAY LINE
Number of functions	1
Number of taps/steps	4
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
programmable delay line	YES
Certification status	Not Qualified
Maximum seat height	4.58 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	17.25 ns
width	7.62 mm
Base Number Matches	1

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3D7424

MONOLITHIC QUAD 4-BIT

PROGRAMMABLE DELAY LINE

(SERIES 3D7424)

FEATURES

•

Four indep’t programmable lines on a single chip

All-silicon CMOS technology

Low quiescent current (5mA typical)

Leading- and trailing-edge accuracy

Vapor phase, IR and wave solderable

Increment range:

0.75ns through 400ns

Delay tolerance:

3% or 2ns (see Table 1)

Line-to-line matching:

1% or 1ns typical

Temperature stability:

±1.5%

typical (-40C to 85C)

Vdd stability:

±0.5%

typical (4.75V to 5.25V)

Minimum input pulse width:

10% of total delay

GND

PACKAGES

VDD

GND

VDD

DIP-14

3D7424-xx

SOIC-14

3D7424D-xx

For mechanical dimensions, click

here

For package marking details, click

here

FUNCTIONAL DESCRIPTION

The 3D7424 device is a small, versatile, quad 4-bit programmable

monolithic delay line. Delay values, programmed via the serial interface,

can be independently varied over 15 equal steps. The step size (in ns) is

determined by the device dash number. Each input is reproduced at the

corresponding output without inversion, shifted in time as per user

selection. For each line, the delay time is given by:

= T0 + A

* TI

PIN DESCRIPTIONS

I1-I4

O1-O4

VDD

GND

Signal Inputs

Signal Outputs

Address Latch In

Serial Clock In

Serial Data In

Serial Data Out

5.0V

Ground

where T0 is the inherent delay, A

is the delay address of the n-th line

and TI is the delay increment (dash number). The desired addresses are

shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The

serial interface can also be used to enable/disable each delay line. The 3D7424 operates at 5 volts and

has a typical T0 of 6ns. The 3D7424 is TTL/CMOS-compatible, capable of sourcing or sinking 4mA loads,

and features both rising- and falling-edge accuracy. The device is offered in a standard 14-pin auto-

insertable DIP and a space saving surface mount 14-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

Part

Number

3D7424-.75

3D7424-1

3D7424-1.5

3D7424-2

3D7424-4

3D7424-5

3D7424-10

3D7424-15

3D7424-20

3D7424-40

3D7424-50

3D7424-100

3D7424-200

3D7424-400

DELAYS & TOLERANCES (NS)

Delay

Inherent

Total

Relative

Step

Delay

Tolerance

.75

0.19 6.0

2.0 17.25

2.0 3% or 0.50ns

1.0

0.25 6.0

2.0

21.0

2.0 3% or 0.50ns

1.5

0.38 6.0

2.0

28.5

2.0 3% or 0.50ns

2.0

0.50 6.0

2.0

36.0

2.0 3% or 0.75ns

4.0

1.00 6.0

2.0

66.0

2.0 3% or 0.75ns

5.0

1.25 6.0

2.0

81.0

2.5 3% or 0.75ns

2.50 6.0

2.0

156

5.0 3% or 1.25ns

3.75 6.0

2.0

231

7.5 3% or 1.88ns

5.00 6.0

2.0

306

10 3% or 2.50ns

10.0 6.0

2.0

606

20 3% or 5.00ns

10.0 6.0

2.0

756

25 3% or 6.25ns

100

12.5 6.0

2.0

1506

50 3% or 12.5ns

200

20.0 6.0

2.0 3006

100 3% or 25.0ns

400

40.0 6.0

2.0 6006

200 3% or 50.0ns

INPUT RESTRICTIONS

Max Frequency

Min Pulse Width

Recom’d Absolute Recom’d

Absolute

19 MHz

166 MHz

26 ns

3.0 ns

16 MHz

166 MHz

32 ns

3.0 ns

12 MHz

111 MHz

43 ns

4.5 ns

9.2 MHz

83 MHz

54 ns

6.0 ns

5.0 MHz

83 MHz

99 ns

6.0 ns

4.1 MHz

66 MHz

122 ns

7.5 ns

2.1 MHz

33 MHz

234 ns

15.0 ns

1.4 MHz

22 MHz

347 ns

22.5 ns

1.0 MHz

16 MHz

459 ns

30.0 ns

550 KHz

8.3 MHz

909 ns

60.0 ns

440 KHz

6.6 MHz

1.2 us

75.0 ns

220 KHz

3.3 MHz

2.3 us

150 ns

110 KHz

1.6 MHz

4.5 us

300 ns

55 KHz

833 KHz

9.0 us

600 ns

NOTE: Any increment between 0.75ns and 400ns not shown is also available as standard

See page 4 for details regarding input restrictions

2006

Data Delay Devices

Doc #06019

6/5/2006

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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