3D7428-0.5 datasheet, PDF - EEWORLD Datasheet

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3D7428-0.5: DescriptionMONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE; Categorylogic logic; File Size194KB，7 Pages; ManufacturerData Delay Devices; Environmental Compliance

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3D7428-0.5 Overview

MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE

3D7428-0.5 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Data Delay Devices
Parts packaging code	DIP
package instruction	DIP-16
Contacts	16
Reach Compliance Code	compliant
series	3D
Input frequency maximum value (fmax)	45 MHz
JESD-30 code	R-PDIP-T16
length	19.305 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	1
Number of taps/steps	255
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	5 mA
programmable delay line	YES
Prop。Delay @ Nom-Sup	138 ns
Certification status	Not Qualified
Maximum seat height	4.58 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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3D7428

MONOLITHIC 8-BIT

PROGRAMMABLE DELAY LINE

(SERIES 3D7428 – LOW NOISE)

FEATURES

•

All-silicon, low-power CMOS technology

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

Leading- and trailing-edge accuracy

Programmable via serial or parallel interface

Increment range:

0.25 through 20.0ns

Delay tolerance:

0.5% (See Table 1)

Supply current:

3mA typical

Temperature stability:

±1.5%

max (-40C to 85C)

Vdd stability:

±0.5%

max (4.75V to 5.25V)

SO/P0

GND

data

delay

devices,

inc.

PACKAGES

VDD

OUT

GND

VDD

OUT



3D7428Z-xx SOIC

SO/P0

GND

VDD

OUT

3D7428-xx DIP

3D7428S-xx SOL

For mechanical dimensions, click

here.

For package marking details, click

here.

FUNCTIONAL DESCRIPTION

The 3D7428 device is a versatile 8-bit programmable monolithic delay

line. The input (IN) is reproduced at the output (OUT) without inversion,

shifted in time as per the user selection. Delay values, programmed

either via the serial or parallel interface, can be varied over 255 equal

steps according to the formula:

i,nom

= T

inh

+ i * T

inc

where i is the programmed address, T

inc

is the delay increment (equal

to the device dash number), and T

inh

is the inherent (address zero)

delay. The device features both rising- and falling-edge accuracy.

PIN DESCRIPTIONS

OUT

P0-P7

VDD

GND

Signal Input

Signal Output

Mode Select

Address Enable

Parallel Data Input

Serial Clock

Serial Data Input

Serial Data Output

+5 Volts

Ground

The all-CMOS 3D7428 integrated circuit has been designed as a reliable, economic alternative to hybrid

TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a surface mount

16-pin SOL. An 8-pin SOIC package is available for applications where the parallel interface is not needed.

TABLE 1: PART NUMBER SPECIFICATIONS

PART

NUMBER

3D7428-0.25

3D7428-0.5

3D7428-1

3D7428-1.5

3D7428-2

3D7428-2.5

3D7428-4

3D7428-5

3D7428-7.5

3D7428-10

3D7428-15

3D7428-20

DELAYS AND TOLERANCES

Inherent

Delay (ns)

10.5

2.0

10.5

2.0

10.5

2.0

10.5

2.0

10.5

2.0

10.5

2.5

13.0

4.0

15.0

5.0

20.0

7.5

23.5

33.0

42.0

Delay

Range (ns)

63.75

0.4

127.5

0.5

255.0

1.0

382.5

1.5

510.0

2.0

637.5

2.5

1020

3.2

1275

4.0

1912.5

6.0

2550

8.0

3825

5100

Delay

Step (ns)

0.25

0.12

0.50

0.25

1.00

0.50

1.50

0.75

2.00

1.00

2.50

1.25

4.00

2.00

5.00

2.50

7.50

3.75

10.0

5.00

15.0

9.00

20.0

12.0

Rec’d Max

Frequency

6.25 MHz

3.12 MHz

1.56 MHz

1.04 MHz

781 KHz

625 KHz

390 KHz

312 KHz

208 KHz

156 KHz

104 KHz

78 KHz

INPUT RESTRICTIONS

Absolute Max

Frequency

77 MHz

45 MHz

22 MHz

15 MHz

11 MHz

9.0 MHz

5.6 MHz

4.5 MHz

3.0 MHz

2.2 MHz

1.5 MHz

1.1 MHz

Rec’d Min

Pulse Width

80.0 ns

160.0 ns

320.0 ns

480.0 ns

640.0 ns

800.0 ns

1280.0 ns

1600.0 ns

2400.0 ns

3200.0 ns

4800.0 ns

6400.0 ns

Absolute Min

Pulse Width

6.5 ns

11.0 ns

22.0 ns

33.0 ns

44.0 ns

55.0 ns

88.0 ns

110.0 ns

165.0 ns

220.0 ns

330.0 ns

440.0 ns

NOTES: Any delay increment between 0.25 and 20 ns not shown is also available as standard.

See application notes section for more details

2004

Data Delay Devices

Doc #03003

5/8/2006

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

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