Freescale Semiconductor
Technical Data
Document Number: MC33889
Rev. 12.0, 3/2007
System Basis Chip with Low
Speed Fault Tolerant CAN
Interface
An SBC device is a monolithic I
C
combining many functions
repeatedly found in standard microcontroller-based systems, e.g.,
protection, diagnostics, communication, power, etc. The 33889 is an
SBC having fully protected, fixed 5.0 V low drop-out regulator, with
current limit, over-temperature pre-warning and reset.
An output drive with sense input is also provided to implement a
second 5.0 V regulator using an external PNP. The 33889 has Normal,
Standby, Stop and Sleep modes; an internally switched high-side
power supply output with two wake-up inputs; programmable timeout
or window watchdog, Interrupt, Reset, SPI input control, and a low-
speed fault tolerant CAN transceiver, compatible with CAN 2.0 A and
B protocols for module-to-module communications. The combination
is an economical solution for power management, high-speed
communication, and control in MCU-based systems.
Features
• VDD1: 5.0 V low drop voltage regulator, current limitation,
overtemperature detection, monitoring and reset function with total
current capability 200 mA
• V
2
: tracking function of VDD1 regulator; control circuitry for external
bipolar ballast transistor for high flexibility in choice of peripheral
voltage and current supply
• Four operational modes
• Low standby current consumption in Stop and Sleep modes
• Built-in low speed 125 kbps fault tolerant CAN physical interface.
• External high voltage wake-up input, associated with HS1 VBAT
switch
• 150 mA output current capability for HS1 VBAT switch allowing
drive of external switches pull-up resistors or relays
• Pb-Free Packaging Designated by Suffix Code EG
33889
SYSTEM BASIS CHIP
DW SUFFIX
EG SUFFIX (PB-FREE)
PLASTIC PACKAGE
98ASB42345B
28-PIN SOICW
ORDERING INFORMATION
Device
MC33889BDW/R2
MCZ33889BEG/R2
MC33889DDW/R2
*MCZ33889DEG/R2
-40°C to 125°C
28 SOICW
Temperature
Range (T
A
)
Package
*
Recommended for new designs
33889
5.0 V
VDD1
GND
VSUP
V2CTRL
V2
HS1
L0
L1
WDOG
RTH
CANH
CANL
RTL
VPWR
V2
MCU
CS
SCLK
MOSI
MISO
SPI
RST
INT
CS
SCLK
MOSI
MISO
TXD
RXD
Local Module Supply
Wake-Up Inputs
Safe Circuits
Twisted
Pair
CAN Bus
Figure 1. 33889 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as
may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations Between the 33889D and 33889B Versions
(1)
Parameters
Differential Receiver, Recessive To Dominant Threshold
(By Definition, V
DIFF
= V
CANH
-V
CANL
)
Symbol
Trait
Min
V
DIFF1
Typ
Max
Differential Receiver, Dominant To Recessive Threshold
(Bus Failures 1, 2, 5)
Min
V
DIFF2
Typ
Max
CANH Output Current (V
CANH
= 0; TX = 0.0)
I
CANH
Min
Typ
Max
CANL Output Current (V
CANL
= 14 V; TX = 0.0)
I
CANL
Min
Typ
Max
Detection threshold for Short circuit to Battery voltage
loop time Tx to Rx, no bus failure, ISO configuration
loop time Tx to Rx, with bus failure, ISO configuration
Vcanh
tLOOPRD
tLOOPRD-F
max
max
max
Device Part Number
MC33889B
(2)
3.2 V
2.6 V
2.1 V
3.2 V
2.6 V
2.1 V
50 mA
75 mA
110 mA
50 mA
90 mA
135 mA
Vsup/2 + 5V
N/A
N/A
N/A
min
typ
max
T2SPI timing
DEVICE BEHAVIOR
CANH or CANL open wire recovery principle
Rx behavior in TermVbat mode
Reference
MC33889B: on page
33
after 4 non
consecutive pulses
after 4 consecutive
pulses
T2spi
min
N/A
30
N/A
not specified, 25us
spec applied
MC33889D
(2)
3.5 V
3.0 V
2.5 V
3.5 V
3.0 V
2.5 V
50 mA
100 mA
130 mA
50 mA
140 mA
170 mA
Vsup/2 + 4.55V
1.5us
1.9us
3.6us
8
16
30
25us
loop time Tx to Rx, with bus failure and +-1.5V gnd shift, tLOOPRD/DR-F+GS
5 node network, ISO configuration
Minimum Dominant time for Wake up on CANL or CANH
(Tem Vbat mode)
tWAKE
Reference
MC33889D: on page
Rx recessive, no pulse Rx recessive, dominant
pulse to signal bus
34
traffic
Notes
1. This datasheet uses the term 33889 in the inclusive sense, referring to both the D version (33889D) and the B version (33689B).
2. The 33889D and 33889B versions are nearly identical. However, where variations in characteristic occur, these items will be separated
onto individual lines.
33889
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
33889 Internal Block Diagram
V2CTRL
V2
VDD1
VSUP
Dual Voltage Regulator
VSUP Voltage Monitor
VDD1 Voltage Monitor
HS1 Control
Oscillator
HS1
L0
L1
Programmable
Wake-Up Inputs
INT
Interrupt
Watchdog
Reset
Mode Control
TX
WDOG
RST
CS
SCLK
MOSI
MISO
GND
V2
SPI
Interface
VSUP
Fault Tolerant
CAN
Transceiver
RX
RTH
CAN H
CAN L
RTL
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
PIN CONNECTIONS
RX
TX
VDD1
RST
INT
GND
GND
GND
GND
V2CTRL
VSUP
HS1
L0
L1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WDOG
CS
MOSI
MISO
SCLK
GND
GND
GND
GND
CANL
CANH
RTL
RTH
V2
Figure 2. 33889 Pin Connections
Table 2. Pin Definitions
A functional description of each pin can be found in the
Functional pin description
section page
24.
Pin
1
2
3
Pin Name
RX
Pin
Function
Output
Input
Power
Output
Formal Name
Receiver Data
Transmitter Data
Voltage Regulator One
Definition
CAN bus receive data output pin
CAN bus receive data input pin
5.0 V pin is a 2% low drop voltage regulator for to the microcontroller
supply.
This is the device reset output pin whose main function is to reset the
MCU.
This output is asserted LOW when an enabled interrupt condition
occurs.
These device ground pins are internally connected to the package lead
frame to provide a 33889-to-PCB thermal path.
Output drive source for the V2 regulator connected to the external series
pass transistor.
Supply input pin.
TX
VDD1
4
5
6 -9,
20 - 23
10
11
RST
INT
GND
V2CTRL
VSUP
Output
Output
Ground
Output
Power
Input
Reset
Interrupt
Ground
Voltage Source 2 Control
Voltage Supply
12
13 - 14
15
16
17
18
19
24
HS1
L0, L1
Output
Input
Input
Output
Output
Output
Output
Input
High-Side Output
Level 0 - 1 Inputs
Voltage Regulator Two
RTH
RTL
CAN High
CAN Low
System Clock
Output of the internal high-side switch.
Inputs from external switches or from logic circuitry.
5.0 V pin is a low drop voltage regulator dedicated to the peripherals
supply.
Pin for connection of the bus termination resistor to CANH.
Pin for connection of the bus termination resistor to CANL.
CAN high output pin.
CAN low output pin.
Clock input pin for the Serial Peripheral Interface (SPI).
V2
RTH
RTL
CANH
CANL
SCLK
33889
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Table 2. Pin Definitions (continued)
A functional description of each pin can be found in the
Functional pin description
section page
24.
Pin
25
26
27
Pin Name
MISO
MOSI
CS
Pin
Function
Output
Input
Input
Formal Name
Master In/Slave Out
Master Out/Slave In
Chip Select
Definition
SPI data sent to the MCU by the 33889. When CS
LOW
is HIGH, the pin
is in the high impedance state.
SPI data received by the 33889.
The CS
LOW
input pin is used with the SPI bus to select the 33889. When
the CS
LOW
is asserted LOW, the 33889 is the selected device of the SPI
bus.
The WDOG output pin is asserted LOW if the software watchdog is not
correctly triggered.
28
WDOG
Output
Watchdog
33889
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
Embedded System
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