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ADM6995L: Description5 PORT 10/100 MB/s SINGLE CHIP ETHERNET SWITCH CONTROLLER; File Size438KB，57 Pages; ManufacturerETC

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ADM6995L Overview

5 PORT 10/100 MB/s SINGLE CHIP ETHERNET SWITCH CONTROLLER

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ADM6995L

5 port 10/100 Mb/s

Single Chip Ethernet Switch Controller

Data Sheet

Version 1.0

ADMtek

com.tw

Information in this document is provided in connection with ADMtek products. ADMtek may make

changes to specifications and product descriptions at any time, without notice. Designers must not rely on

the absence or characteristics of any features or instructions marked “reserved” or “undefined”. ADMtek

reserves these for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them

The products may contain design defects or errors know as errata, which may cause the product to deviate

from published specifications. Current characterized errata are available on request. To obtain the latest

documentation please contact your local ADMtek sales office or visit ADMtek’s website at

http://www.ADMtek.com.tw

*Third-party brands and names are the property of their respective owners.

Copyright

ADMtek Inc.

V1.0

Table of Contents

Chapter 1 Product Overview ........................................................................................ 1-1

1.1

Overview.......................................................................................................... 1-1

1.2

Features ............................................................................................................ 1-2

1.3

Block Diagram ................................................................................................. 1-3

1.4

Abbreviations................................................................................................... 1-3

1.5 Conventions ........................................................................................................... 1-5

1.5.1

Data Lengths............................................................................................ 1-5

1.5.2

Pin Types.................................................................................................. 1-5

1.5.2

Chapter 2 Interface Description ................................................................................... 2-1

2.1

Pin Diagram ..................................................................................................... 2-1

2.2

Pin Description by Function ............................................................................ 2-2

2.2.1

Twisted Pair Interface.............................................................................. 2-2

2.2.2

Setting ...................................................................................................... 2-2

2.2.3

LED Interface........................................................................................... 2-3

2.2.4

EEPROM/Management Interface ............................................................ 2-4

2.2.5

Power/Ground, 48 pins............................................................................ 2-4

2.2.6

MISC ........................................................................................................ 2-5

Chapter 3 Function Description ................................................................................... 3-1

3.1

Functional Descriptions ................................................................................... 3-1

3.2

10/100M PHY Block ....................................................................................... 3-1

3.3

100Base-X Module .......................................................................................... 3-1

3.4

100Base-X Receiver ........................................................................................ 3-1

3.4.1

A/D Converter.......................................................................................... 3-2

3.4.2

Adaptive Equalizer and timing Recovery Module ................................... 3-3

3.4.3

NRZI/NRZ and Serial/Parallel Decoder.................................................. 3-3

3.4.4

Data De-scrambling................................................................................. 3-3

3.4.5

Symbol Alignment .................................................................................... 3-3

3.4.6

Symbol Decoding ..................................................................................... 3-3

3.4.7

Valid Data Signal..................................................................................... 3-4

3.4.8

Receive Errors ......................................................................................... 3-4

3.4.9

100Base-X Link Monitor.......................................................................... 3-4

3.4.10

Carrier Sense ........................................................................................... 3-4

3.4.11

Bad SSD Detection................................................................................... 3-5

3.4.12

Far-End Fault .......................................................................................... 3-5

3.5

100Base-TX Transceiver ................................................................................. 3-5

3.5.1

Transmit Drivers...................................................................................... 3-5

3.5.2

Twisted-Pair Receiver.............................................................................. 3-6

3.6

10Base-T Module............................................................................................. 3-6

3.6.1

Operation Modes ..................................................................................... 3-6

3.6.2

Manchester Encoder/Decoder ................................................................. 3-6

3.6.3

Transmit Driver and Receiver ................................................................. 3-7

3.6.4

Smart Squelch .......................................................................................... 3-7

3.7

Carrier Sense.................................................................................................... 3-7

3.8

Jabber Function................................................................................................ 3-7

ADM6995L

ADMtek Inc.

3.9

Link Test Function........................................................................................... 3-8

3.10

Automatic Link Polarity Detection.............................................................. 3-8

3.11

Clock Synthesizer ........................................................................................ 3-8

3.12

Auto Negotiation.......................................................................................... 3-8

3.13

Memory Block ............................................................................................. 3-9

3.14

Switch Functional Description..................................................................... 3-9

3.15

Basic Operation............................................................................................ 3-9

3.15.1

Address Learning ................................................................................... 3-10

3.15.2

Address Recognition and Packet Forwarding ....................................... 3-10

3.15.3

Address Aging ........................................................................................ 3-10

3.15.4

Back off Algorithm ................................................................................. 3-11

3.15.5

Inter-Packet Gap (IPG) ......................................................................... 3-11

3.15.6

Illegal Frames........................................................................................ 3-11

3.15.7

Half Duplex Flow Control ..................................................................... 3-11

3.15.8

Full Duplex Flow Control...................................................................... 3-11

3.15.9

Broadcast Storm filter............................................................................ 3-11

3.16 Auto TP MDIX function................................................................................ 3-12

3.17

Port Locking............................................................................................... 3-12

3.18

VLAN setting & Tag/Untag & port-base VLAN ...................................... 3-12

3.19

Priority Setting ........................................................................................... 3-13

3.20

LED Display .............................................................................................. 3-14

Chapter 4 Register Description .................................................................................... 4-1

4.1

EEPROM Content............................................................................................ 4-1

4.2

EEPROM Register Map................................................................................... 4-1

4.3

EEPROM Register ........................................................................................... 4-2

4.3.1

Signature Register, offset: 0x00h.............................................................. 4-2

4.3.2

Configuration Registers, offset: 0x01h ~ 0x09h ...................................... 4-3

4.3.3

Reserved Register, offset: 0x0ah.............................................................. 4-3

4.3.4

Configuration Register, offset: 0x0bh...................................................... 4-4

4.3.5

Reserved Register, offset: 0x0ch~0x0dh .................................................. 4-4

4.3.6

VLAN priority Map Register, offset: 0x0eh ............................................. 4-4

4.3.7

TOS priority Map Register, offset: 0x0fh................................................. 4-4

4.3.8

Packet with Priority: Normal packet content .......................................... 4-5

4.3.9

VLAN Packet............................................................................................ 4-5

4.3.10

TOS IP Packet.......................................................................................... 4-6

4.3.11

Miscellaneous Configuration Register, offset: 0x10h.............................. 4-6

4.3.12

VLAN mode select Register, offset: 0x11h............................................... 4-7

4.3.13

Miscellaneous Configuration register, offset: 0x12h .............................. 4-7

4.3.14

VLAN mapping table registers, offset: 0x22h ~ 0x13h ............................ 4-8

4.3.15 Reserved Register, offset: 0x27h ~ 0x23h................................................ 4-8

4.3.16 Port0 PVID bit 11 ~ 4 Configuration Register, offset: 0x28h ................. 4-8

4.3.17 Port1 PVID bit 11 ~ 4 Configuration Register, offset: 0x29h ................. 4-8

4.3.18 Port2 PVID bit 11~4 Configuration Register, offset: 0x2ah ................... 4-9

4.3.19 Port3, 4 PVID bit 11~4 Configuration Register, offset: 0x2bh ............... 4-9

4.3.20 VLAN group shift bits Configuration Register, offset: 0x2ch .................. 4-9

4.3.21 Reserved Register, offset: 0x2dh.............................................................. 4-9

V1.0

ADM6995L

ADMtek Inc.

4.3.22

Reserved Register, offset: 0x2eh ............................................................ 4-10

4.3.23

PHY Restart, offset: 0x2fh...................................................................... 4-10

4.3.24

Miscellaneous Configuration Register, offset: 0x30h............................ 4-10

4.3.25

Bandwidth Control Register0~3, offset: 0x31h...................................... 4-10

4.3.26

Bandwidth Control Register 4~5, offset: 0x32h..................................... 4-11

4.3.27

Bandwidth Control Enable Register, offset: 0x33h ................................ 4-11

4.4

EEPROM Access ........................................................................................... 4-12

4.5

Serial Register Map........................................................................................ 4-13

4.6

Serial Register Description ............................................................................ 4-15

4.6.1

Chip Identifier Register, offset: 0x00h................................................... 4-15

4.6.2

Port Status 0 Register, offset: 0x01h ..................................................... 4-15

4.6.3

Port Status 1 Register, offset: 0x02h ..................................................... 4-17

4.6.4

Cable Broken Status Register, offset: 0x03h.......................................... 4-17

4.6.5

Over Flow Flag 0 Register, offset: 0x3ah.............................................. 4-17

4.6.6

Over Flow Flag 0: Register 0x3bh ........................................................ 4-18

4.6.7

Over Flow Flag 2 Register, offset: 0x3ch.............................................. 4-18

4.7

Serial Interface Timing .................................................................................. 4-20

Chapter 5 Electrical Specification................................................................................ 5-1

5.1

TX/FX Interface............................................................................................... 5-1

5.1.1

TP Interface ............................................................................................. 5-1

5.1.2

FX Interface ............................................................................................. 5-1

5.2

DC Characteristics ........................................................................................... 5-2

5.2.1

Absolute Maximum Rating....................................................................... 5-2

5.2.2

Recommended Operating Conditions ...................................................... 5-2

5.2.3

DC Electrical Characteristics for 3.3V Operation .................................. 5-2

5.3

AC Characteristics ........................................................................................... 5-3

5.3

AC Characteristics ........................................................................................... 5-3

5.3.1

Power On Reset........................................................................................ 5-3

5.3.2

EEPROM Interface Timing...................................................................... 5-3

5.3.3

GPSI(7-wire) Input Timing ...................................................................... 5-4

5.3.4

GPSI(7-wire) Output Timing ................................................................... 5-4

Chapter 6 Packaging...................................................................................................... 6-1

6.1

128 Pin PQFP Outside Dimension................................................................... 6-1

V1.0

ADM6995L

iii

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